Seth/kernel_amazon_mt8127-common
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Add required changes for austin and ford

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This commit is contained in:
ggow
2019-04-21 09:20:06 +01:00
parent 43fd89a550
commit fddef9b0e1
904 changed files with 133095 additions and 95488 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/configs/austin_defconfig
+3316
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File diff suppressed because it is too large Load Diff
arch/arm/configs/ford_defconfig
+3306
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File diff suppressed because it is too large Load Diff
arch/arm/kernel/process.c
+1 -9
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@@ -61,10 +61,6 @@ static const char *isa_modes[] = {
"ARM" , "Thumb" , "Jazelle", "ThumbEE"
};
//[BUGFIX]-Add-BEGIN by SCDTABLET.(fangyou.wang),10/10/2015,1097303,
//auto reboot after power off
extern void force_enable_uart_log(void);
//[BUGFIX]-Add-END by SCDTABLET.(fangyou.wang)
#ifdef CONFIG_SMP
void arch_trigger_all_cpu_backtrace(void)
{
@@ -334,11 +330,7 @@ void machine_power_off(void)
/* Disable interrupts first */
local_irq_disable();
local_fiq_disable();
//[BUGFIX]-Add-BEGIN by SCDTABLET.(fangyou.wang),10/10/2015,1097303,
//auto reboot after power off
force_enable_uart_log();
//[BUGFIX]-Add-END by SCDTABLET.(fangyou.wang)
smp_send_stop();
if(reboot_pid > 1)
{
arch/arm/mach-mt8127/Makefile
-2
View File
@@ -56,9 +56,7 @@ ccflags-y += -I$(MTK_PATH_PLATFORM)/drivers/power \
obj-y += mt_spm.o mt_spm_sleep.o mt_spm_mtcmos.o
ccflags-$(CONFIG_MTK_IN_HOUSE_TEE_SUPPORT) += -I$(srctree)/include/trustzone/
obj-y += mt_sleep.o
#obj-y += mt_cpufreq.o mt_gpufreq.o mt_cpu_ss.o
obj-y += mt_cpufreq.o mt_cpu_ss.o
obj-y += mt_emifreq.o
obj-y += mt_dormant.o cpu_dormant.o
obj-y += mt_dcm.o mt_idle.o
obj-y += mt_clkmgr_common.o
arch/arm/mach-mt8127/camera_isp.c
+50 -113
View File
@@ -2047,7 +2047,7 @@ static MBOOL ISP_BufWrite_Add(MUINT32 Size,MUINT8 *pData)
{
if(g_IspInfo.BufInfo.Write[i].Status == ISP_BUF_STATUS_HOLD)
{
if((g_IspInfo.BufInfo.Write[i].Size + Size) > ISP_BUF_SIZE_WRITE)
if ((Size > ISP_BUF_SIZE_WRITE) || ((g_IspInfo.BufInfo.Write[i].Size + Size) > ISP_BUF_SIZE_WRITE))
{
LOG_ERR("i(%d), BufWriteSize(%d) + Size(%d) > %d",i,g_IspInfo.BufInfo.Write[i].Size,Size,ISP_BUF_SIZE_WRITE);
return MFALSE;
@@ -5102,99 +5102,38 @@ static struct platform_driver IspDriver =
*
********************************************************************************/
static MINT32 ISP_DumpRegToProc(
char *pPage,
char **ppStart,
off_t off,
MINT32 Count,
MINT32 *pEof,
MVOID *pData)
struct file *pFile,
char *pStart,
size_t Off,
loff_t *Count)
{
char *p = pPage;
MINT32 Length = 0;
MUINT32 i = 0;
MINT32 ret = 0;
LOG_DBG("pPage(0x%08x),off(%d),Count(%d)", (MUINT32)pPage, (MUINT32)off, Count);
p += sprintf(p, " MT ISP Register\n");
p += sprintf(p, "====== top ====\n");
for(i = 0x0; i <= 0x1AC; i += 4)
{
p += sprintf(p,"+0x%08x 0x%08x\n", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
}
p += sprintf(p,"====== dma ====\n");
for(i = 0x200; i <= 0x3D8; i += 4)
{
p += sprintf(p,"+0x%08x 0x%08x\n\r", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
}
p += sprintf(p,"====== tg ====\n");
for(i = 0x400; i <= 0x4EC; i += 4)
{
p += sprintf(p,"+0x%08x 0x%08x\n", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
}
p += sprintf(p,"====== cdp (including EIS) ====\n");
for(i = 0xB00; i <= 0xDE0; i += 4)
{
p += sprintf(p,"+0x%08x 0x%08x\n", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
}
p += sprintf(p,"====== seninf ====\n");
for(i = 0x4000; i <= 0x40C0; i += 4)
{
p += sprintf(p,"+0x%08x 0x%08x\n", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
}
for(i = 0x4100; i <= 0x41BC; i += 4)
{
p += sprintf(p,"+0x%08x 0x%08x\n", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
}
for(i = 0x4300; i <= 0x4310; i += 4)
{
p += sprintf(p,"+0x%08x 0x%08x\n", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
}
for(i = 0x43A0; i <= 0x43B0; i += 4)
{
p += sprintf(p,"+0x%08x 0x%08x\n", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
}
for(i = 0x4400; i <= 0x4424; i += 4)
{
p += sprintf(p,"+0x%08x 0x%08x\n", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
}
for(i = 0x4500; i <= 0x4520; i += 4)
{
p += sprintf(p,"+0x%08x 0x%08x\n", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
}
p += sprintf(p,"====== 3DNR ====\n");
for(i = 0x4F00; i <= 0x4F38; i += 4)
{
p += sprintf(p,"+0x%08x 0x%08x\n", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
}
*ppStart = pPage + off;
Length = p - pPage;
if(Length > off)
{
Length -= off;
}
else
{
Length = 0;
}
char *buffer_log = kmalloc(1000*sizeof(unsigned int), GFP_KERNEL);
ret = Length < Count ? Length : Count;
if (buffer_log == NULL) {
LOG_ERR("kmalloc fail");
kfree(buffer_log);
return -EFAULT;
}
LOG_DBG("ret(%d)", ret);
return ret;
if (*Count > 0) {
kfree(buffer_log);
return 0;
}
Length += sprintf(buffer_log, "MT ISP Register\n");
Length += sprintf(buffer_log + Length,"+0x%08x 0x%08x\n", ISP_ADDR + 0x4,ISP_RD32((void *)(ISP_ADDR + 0x4)));
if (copy_to_user(pStart, buffer_log, Length)) {
LOG_ERR("copy_to_user fail");
kfree(buffer_log);
return -EFAULT;
}
*Count = *Count + Length;
kfree(buffer_log);
return Length;
}
/*******************************************************************************
@@ -5235,38 +5174,36 @@ static MINT32 ISP_RegDebug(
static MUINT32 proc_regOfst = 0;
static MINT32 CAMIO_DumpRegToProc(
char *pPage,
char **ppStart,
off_t off,
MINT32 Count,
MINT32 *pEof,
MVOID *pData)
struct file *pFile,
char *pStart,
size_t Off,
loff_t *Count)
{
char *p = pPage;
MINT32 Length = 0;
MINT32 ret = 0;
LOG_DBG("pPage(0x%08x),off(%d),Count(%d)", (MUINT32)pPage, (MINT32)off, Count);
p += sprintf(p,"reg_0x%08X = 0x%X \n", ISP_ADDR_CAMINF + proc_regOfst , ioread32((void *)(ISP_ADDR_CAMINF + proc_regOfst)));
char *buffer_log = kmalloc(1000*sizeof(unsigned int), GFP_KERNEL);
*ppStart = pPage + off;
Length = p - pPage;
if(Length > off)
{
Length -= off;
if (buffer_log == NULL) {
LOG_ERR("kmalloc fail");
kfree(buffer_log);
return -EFAULT;
}
else
{
Length = 0;
if (*Count > 0) {
kfree(buffer_log);
return 0;
}
//
ret = Length < Count ? Length : Count;
Length += sprintf(buffer_log,"reg_0x%08X = 0x%X \n", ISP_ADDR_CAMINF + proc_regOfst , ioread32((void *)(ISP_ADDR_CAMINF + proc_regOfst)));
if (copy_to_user(pStart, buffer_log, Length)) {
LOG_ERR("copy_to_user fail");
kfree(buffer_log);
return -EFAULT;
}
LOG_DBG("ret(%d)", ret);
return ret;
*Count = *Count + Length;
kfree(buffer_log);
return Length;
}
/*******************************************************************************
arch/arm/mach-mt8127/camera_sysram.c
+69 -53
View File
@@ -917,14 +917,16 @@ static int SYSRAM_mmap(
struct vm_area_struct* pVma)
{
//LOG_MSG("");
long length = 0;
unsigned long length = 0;
MUINT32 pfn=0x0;
pVma->vm_page_prot = pgprot_noncached(pVma->vm_page_prot);
length=(long)(pVma->vm_end - pVma->vm_start);
length = pVma->vm_end - pVma->vm_start;
pfn=pVma->vm_pgoff<<PAGE_SHIFT;//page from number, physical address of kernel memory
LOG_WRN("pVma->vm_pgoff(0x%x),phy(0x%x),pVmapVma->vm_start(0x%x),pVma->vm_end(0x%x),length(0x%x)",\
pVma->vm_pgoff,pVma->vm_pgoff<<PAGE_SHIFT,pVma->vm_start,pVma->vm_end,length);
if((length>ISP_VALID_REG_RANGE) || (pfn<IMGSYS_BASE_ADDR) || (pfn>(IMGSYS_BASE_ADDR+ISP_VALID_REG_RANGE)))
if((length>ISP_VALID_REG_RANGE) || (pfn<IMGSYS_BASE_ADDR) || (pfn>(IMGSYS_BASE_ADDR+ISP_VALID_REG_RANGE) || pVma->vm_end <= pVma->vm_start))
{
LOG_ERR("mmap range error : vm_start(0x%x),vm_end(0x%x),length(0x%x),pfn(0x%x)!",pVma->vm_start,pVma->vm_end,length,pfn);
return -EAGAIN;
@@ -1257,35 +1259,46 @@ static struct platform_driver SysramPlatformDriver =
};
//------------------------------------------------------------------------------
static int SYSRAM_DumpLayoutToProc(
char* pPage,
char** ppStart,
off_t Off,
int Count,
int* pEof,
void* pData)
struct file *pFile,
char *pStart,
size_t Off,
loff_t *Count)
{
char *p = pPage;
MUINT32 len = 0;
MINT32 Length = 0;
MUINT32 Index = 0;
SYSRAM_MEM_NODE_STRUCT* pCurrNode = NULL;
//
p += sprintf(p, "\n[SYSRAM_DumpLayoutToProc]\n");
p += sprintf(p, "AllocatedTbl = 0x%08lX\n",Sysram.AllocatedTbl);
p += sprintf(p, "=========================================\n" );
char *buffer_log = kmalloc(1000*sizeof(unsigned int), GFP_KERNEL);
if (buffer_log == NULL) {
LOG_ERR("kmalloc fail");
kfree(buffer_log);
return -EFAULT;
}
if (*Count > 0) {
kfree(buffer_log);
return 0;
}
Length += sprintf(buffer_log, "\n[SYSRAM_DumpLayoutToProc]\n");
Length += sprintf(buffer_log + Length, "AllocatedTbl = 0x%08lX\n",Sysram.AllocatedTbl);
Length += sprintf(buffer_log + Length, "=========================================\n" );
for (Index = 0; Index < SYSRAM_MEM_BANK_AMOUNT; Index++)
{
p += sprintf(p, "\n [Mem Pool %ld] (IndexTbl, UserCount)=(%lX, %ld)\n",
Length += sprintf(buffer_log + Length, "\n [Mem Pool %ld] (IndexTbl, UserCount)=(%lX, %ld)\n",
Index,
SysramMemPoolInfo[Index].IndexTbl,
SysramMemPoolInfo[Index].UserCount);
p += sprintf(p, "[Locked Time] [Owner Offset Size Index pCurrent pPrevious pNext] [pid tgid] [Proc Name / Owner Name]\n");
Length += sprintf(buffer_log + Length, "[Locked Time] [Owner Offset Size Index pCurrent pPrevious pNext] [pid tgid] [Proc Name / Owner Name]\n");
pCurrNode = &SysramMemPoolInfo[Index].pMemNode[0];
while ( NULL != pCurrNode )
{
SYSRAM_USER_ENUM const User = pCurrNode->User;
if ( SYSRAM_IsBadOwner(User) )
{
p += sprintf(p,
Length += sprintf(buffer_log + Length,
"------------ --------"
" %2d\t0x%05lX 0x%05lX %ld %p %p\t%p\n",
pCurrNode->User,
@@ -1300,7 +1313,7 @@ static int SYSRAM_DumpLayoutToProc(
else
{
SYSRAM_USER_STRUCT*const pUserInfo = &Sysram.UserInfo[User];
p += sprintf(p,
Length += sprintf(buffer_log + Length,
"%5lu.%06lu"
" %2d\t0x%05lX 0x%05lX %ld %p %p\t%p"
" %-4d %-4d \"%s\" / \"%s\"\n",
@@ -1321,49 +1334,52 @@ static int SYSRAM_DumpLayoutToProc(
pCurrNode = pCurrNode->pNext;
};
}
//
*ppStart = pPage + Off;
len = p - pPage;
if(len > Off)
{
len -= Off;
if (copy_to_user(pStart, buffer_log, Length)) {
LOG_ERR("copy_to_user fail");
kfree(buffer_log);
return -EFAULT;
}
else
{
len = 0;
}
//
return len < Count ? len : Count;
*Count = *Count + Length;
kfree(buffer_log);
return Length;
}
//------------------------------------------------------------------------------
static int SYSRAM_ReadFlag(
char* pPage,
char** ppStart,
off_t Off,
int Count,
int* pEof,
void* pData)
struct file *pFile,
char *pStart,
size_t Off,
loff_t *Count)
{
char *p = pPage;
MUINT32 len = 0;
//
p += sprintf(p, "\r\n[SYSRAM_ReadFlag]\r\n");
p += sprintf(p, "=========================================\r\n" );
p += sprintf(p, "Sysram.DebugFlag = 0x%08lX\r\n",Sysram.DebugFlag);
*ppStart = pPage + Off;
MINT32 Length = 0;
len = p - pPage;
if(len > Off)
{
len -= Off;
char *buffer_log = kmalloc(1000*sizeof(unsigned int), GFP_KERNEL);
if (buffer_log == NULL) {
LOG_ERR("kmalloc fail");
kfree(buffer_log);
return -EFAULT;
}
else
{
len = 0;
if (*Count > 0) {
kfree(buffer_log);
return 0;
}
//
return len < Count ? len : Count;
Length += sprintf(buffer_log, "\r\n[SYSRAM_ReadFlag]\r\n");
Length += sprintf(buffer_log + Length, "Sysram.DebugFlag = 0x%08lX\r\n",Sysram.DebugFlag);
if (copy_to_user(pStart, buffer_log, Length)) {
LOG_ERR("copy_to_user fail");
kfree(buffer_log);
return -EFAULT;
}
*Count = *Count + Length;
kfree(buffer_log);
return Length;
}
//------------------------------------------------------------------------------
static int SYSRAM_WriteFlag(
arch/arm/mach-mt8127/core.c
+35 -4
View File
@@ -15,6 +15,8 @@
#include <mach/mt_reg_base.h>
#include <mach/irqs.h>
#include <linux/version.h>
#include <mach/mt_spm_sleep.h>
#include <mach/mt_spm.h>
extern void arm_machine_restart(char mode, const char *cmd);
extern struct sys_timer mt6582_timer;
@@ -25,6 +27,32 @@ extern struct smp_operations mt65xx_smp_ops;
extern void mt_fixup(struct tag *tags, char **cmdline, struct meminfo *mi);
extern void mt_reserve(void);
/* Added by haitaoy@amazon.com for AUSTINPLAT-1413. */
struct mt_wake_event_map mt8127_event_map[] = {
{
.domain = "SPM",
.code = 10, /* for WAKE_SRC_CONN */
.we = WEV_WIFI,
.irq = 10,
},
/* Examples for tracing other types of wake source or event. */
#if 0
{
.domain = "SPM",
.code = 21, /* for WAKE_SRC_THERM */
.we = WEV_THERM,
.irq = 21,
},
{
.domain = "IRQ",
.code = MT_CONN2AP_BTIF_WAKEUP_IRQ_ID, /* BTIF_WAKEUP_IRQ_ID */
.we = WEV_BT,
.irq = MT_CONN2AP_BTIF_WAKEUP_IRQ_ID, /* BTIF_WAKEUP_IRQ_ID */
},
#endif
{ /*empty*/ }
};
void __init mt_init(void)
{
/* enable bus out of order command queue to enhance boot time */
@@ -35,6 +63,9 @@ void __init mt_init(void)
writel(opt, IOMEM(MCU_BIU_BASE));
dsb();
#endif
/* Added by haitaoy@amazon.com for AUSTINPLAT-1413. */
spm_set_wakeup_event_map(mt8127_event_map);
}
#if defined(CONFIG_TRUSTONIC_TEE_SUPPORT) || defined(CONFIG_MTK_IN_HOUSE_TEE_SUPPORT)
@@ -90,7 +121,7 @@ static struct map_desc mt_io_desc[] __initdata =
.virtual = SYSRAM_BASE,
.pfn = __phys_to_pfn(0x00200000),
.length = SZ_128K,
.type = MT_MEMORY_NONCACHED
.type = MT_DEVICE
},
{
.virtual = G3D_CONFIG_BASE,
@@ -134,7 +165,7 @@ static struct map_desc mt_io_desc[] __initdata =
.virtual = INTER_SRAM,
.pfn = __phys_to_pfn(0x00100000),
.length = SZ_64K,
.type = MT_MEMORY_NONCACHED
.type = MT_DEVICE
},
#else
{
@@ -162,7 +193,7 @@ static struct map_desc mt_io_desc[] __initdata =
.virtual = SYSRAM_BASE,
.pfn = __phys_to_pfn(0x00200000),
.length = SZ_128K,
.type = MT_MEMORY_NONCACHED
.type = MT_DEVICE
},
{
.virtual = DISPSYS_BASE,
@@ -199,7 +230,7 @@ static struct map_desc mt_io_desc[] __initdata =
.virtual = INTER_SRAM,
.pfn = __phys_to_pfn(0x00100000),
.length = SZ_64K,
.type = MT_MEMORY_NONCACHED
.type = MT_DEVICE
},
#endif
};
arch/arm/mach-mt8127/ford/Makefile
Executable
+60
View File
@@ -0,0 +1,60 @@
include $(srctree)/drivers/misc/mediatek/Makefile.custom
ifneq ($(CONFIG_ARCH_MTK_PROJECT),)
ARCH_MTK_PROJECT := $(shell echo $(CONFIG_ARCH_MTK_PROJECT))
obj-y += core/
ifeq ($(CONFIG_AUSTIN_PROJECT),y)
obj-y += dct/dct_austin/
else
obj-y += dct/dct/
endif
endif
ifeq ($(CONFIG_CUSTOM_KERNEL_ACCELEROMETER),y)
obj-y += accelerometer/
endif
ifeq ($(CONFIG_MTK_KXTJ2_1009),y)
obj-y += accelerometer/KXTJ2_1009/
endif
ifeq ($(CONFIG_MTK_BMA253),y)
obj-y += accelerometer/BMA253/
endif
ifeq ($(CONFIG_MTK_MC3410),y)
obj-y += accelerometer/MC3410-NEW/
endif
ifeq ($(CONFIG_CUSTOM_KERNEL_GYROSCOPE),y)
obj-y += gyroscope/
endif
ifeq ($(CONFIG_CUSTOM_KERNEL_MAGNETOMETER),y)
obj-y += magnetometer/
endif
ifeq ($(CONFIG_CUSTOM_KERNEL_ALSPS),y)
obj-y += alsps/
endif
obj-y += cam_cal/
obj-y += camera/camera/
obj-y += eeprom/
###obj-y += flashlight/
obj-y += flashlight/constant_flashlight/
obj-y += headset/
###zbj-y += imgsensor/
obj-y += keypad/
obj-y += leds/
obj-y += lens/
obj-y += sound/
###obj-y += ssw/
obj-y += touchpanel/
obj-y += vibrator/
#obj-y += wmt/
ifeq ($(CONFIG_MTK_HDMI_SUPPORT),y)
obj-y +=hdmi/
endif
arch/arm/mach-mt8127/ford/accdet/accdet_custom.h
+14
View File
@@ -0,0 +1,14 @@
struct headset_mode_settings{
int pwm_width; //pwm frequence
int pwm_thresh; //pwm duty
int fall_delay; //falling stable time
int rise_delay; //rising stable time
int debounce0; //hook switch or double check debounce
int debounce1; //mic bias debounce
int debounce3; //plug out debounce
};
//key press customization: long press time
struct headset_key_custom{
int headset_long_press_time;
};
arch/arm/mach-mt8127/ford/accdet/accdet_custom_def.h
+15
View File
@@ -0,0 +1,15 @@
// use accdet + EINT solution
#define ACCDET_EINT
// support multi_key feature
#define ACCDET_MULTI_KEY_FEATURE
// after 5s disable accdet
#define ACCDET_LOW_POWER
//#define ACCDET_PIN_RECOGNIZATION
#define ACCDET_28V_MODE
#define ACCDET_SHORT_PLUGOUT_DEBOUNCE
#define ACCDET_SHORT_PLUGOUT_DEBOUNCE_CN 20
//extern struct headset_mode_settings* get_cust_headset_settings(void);
//extern int get_long_press_time_cust(void);
arch/arm/mach-mt8127/ford/accelerometer/BMA253/Makefile
+4
View File
@@ -0,0 +1,4 @@
include $(srctree)/drivers/misc/mediatek/Makefile.custom
obj-y := bma253_cust_acc.o
arch/arm/mach-mt8127/ford/accelerometer/BMA253/bma253_cust_acc.c
+30
View File
@@ -0,0 +1,30 @@
#include <linux/types.h>
#include <cust_acc.h>
#include <mach/mt_pm_ldo.h>
/*---------------------------------------------------------------------------*/
static int cust_acc_power(struct acc_hw *hw, unsigned int on, char *devname)
{
if (hw->power_id == MT65XX_POWER_NONE)
return 0;
if (on)
return hwPowerOn(hw->power_id, hw->power_vol, devname);
else
return hwPowerDown(hw->power_id, devname);
}
/*---------------------------------------------------------------------------*/
static struct acc_hw cust_acc_hw = {
.i2c_num = 2,
.direction = 5,
.power_id = MT65XX_POWER_NONE, /*!< LDO is not used */
.power_vol = VOL_DEFAULT, /*!< LDO is not used */
.firlen = 0, /*!< don't enable low pass fileter */
.power = cust_acc_power,
};
/*---------------------------------------------------------------------------*/
struct acc_hw *get_bma253_cust_acc_hw(void)
{
return &cust_acc_hw;
}
drivers/misc/mediatek/imgsensor/src/mt8127/gc2355_mipi_raw/Makefile → arch/arm/mach-mt8127/ford/accelerometer/KXTJ2_1009/Makefile
Regular → Executable
+1 -1
View File
@@ -1,4 +1,4 @@
include $(srctree)/drivers/misc/mediatek/Makefile.custom
obj-y += gc2355mipi_Sensor.o
obj-y := kxtj2_1009_cust_acc.o
arch/arm/mach-mt8127/ford/accelerometer/KXTJ2_1009/kxtj2_1009_cust_acc.c
+28
View File
@@ -0,0 +1,28 @@
#include <linux/types.h>
#include <cust_acc.h>
#include <mach/mt_pm_ldo.h>
/*---------------------------------------------------------------------------*/
static int cust_acc_power(struct acc_hw *hw, unsigned int on, char* devname)
{
if (hw->power_id == MT65XX_POWER_NONE)
return 0;
if (on)
return hwPowerOn(hw->power_id, hw->power_vol, devname);
else
return hwPowerDown(hw->power_id, devname);
}
/*---------------------------------------------------------------------------*/
static struct acc_hw cust_acc_hw = {
.i2c_num = 2,
.direction = 5,
.power_id = MT65XX_POWER_NONE, /*!< LDO is not used */
.power_vol= VOL_DEFAULT, /*!< LDO is not used */
.firlen = 3, /*!< don't enable low pass fileter */
.power = cust_acc_power,
};
/*---------------------------------------------------------------------------*/
struct acc_hw* get_kxtj2_1009_cust_acc_hw(void)
{
return &cust_acc_hw;
}
arch/arm/mach-mt8127/ford/accelerometer/MC3410-NEW/Makefile
Executable
+4
View File
@@ -0,0 +1,4 @@
include $(srctree)/drivers/misc/mediatek/Makefile.custom
obj-y := mc3410_cust_acc.o
arch/arm/mach-mt8127/ford/accelerometer/MC3410-NEW/mc3410_cust_acc.c
+19
View File
@@ -0,0 +1,19 @@
#include <linux/types.h>
#include <cust_acc.h>
#include <mach/mt_pm_ldo.h>
/*---------------------------------------------------------------------------*/
static struct acc_hw cust_acc_hw = {
.i2c_num = 2,
.direction = 7,
.power_id = MT65XX_POWER_NONE, /*!< LDO is not used */
.power_vol= VOL_DEFAULT, /*!< LDO is not used */
.firlen = 0, //old value 16 /*!< don't enable low pass fileter */
.is_batch_supported = false,
};
/*---------------------------------------------------------------------------*/
struct acc_hw* get_mc3410_cust_acc_hw(void)
{
return &cust_acc_hw;
}
drivers/misc/mediatek/dum-char/mt8127/Makefile → arch/arm/mach-mt8127/ford/accelerometer/Makefile
+1 -1
View File
@@ -1,3 +1,3 @@
include $(srctree)/drivers/misc/mediatek/Makefile.custom
obj-y := cust_acc.o
obj-y := dumchar.o
arch/arm/mach-mt8127/ford/accelerometer/accel.c
+795
View File
@@ -0,0 +1,795 @@
#include "accel.h"
static struct acc_context *acc_context_obj = NULL;
static struct acc_init_info* gsensor_init_list[MAX_CHOOSE_G_NUM]= {0}; //modified
static void acc_early_suspend(struct early_suspend *h);
static void acc_late_resume(struct early_suspend *h);
static void acc_work_func(struct work_struct *work)
{
struct acc_context *cxt = NULL;
int out_size;
//hwm_sensor_data sensor_data;
int x,y,z,status,div;
int64_t nt;
struct timespec time;
int err, idx;
cxt = acc_context_obj;
if(NULL == cxt->acc_data.get_data)
{
ACC_LOG("acc driver not register data path\n");
}
time.tv_sec = time.tv_nsec = 0;
time = get_monotonic_coarse();
nt = time.tv_sec*1000000000LL+time.tv_nsec;
err = cxt->acc_data.get_data(&x,&y,&z,&status);
if(err)
{
ACC_ERR("get acc data fails!!\n" );
goto acc_loop;
}
else
{
{
if( 0 == x && 0==y
&& 0 == z)
{
goto acc_loop;
}
cxt->drv_data.acc_data.values[0] = x;
cxt->drv_data.acc_data.values[1] = y;
cxt->drv_data.acc_data.values[2] = z;
cxt->drv_data.acc_data.status = status;
cxt->drv_data.acc_data.time = nt;
}
}
if(true == cxt->is_first_data_after_enable)
{
cxt->is_first_data_after_enable = false;
//filter -1 value
if(ACC_INVALID_VALUE == cxt->drv_data.acc_data.values[0] ||
ACC_INVALID_VALUE == cxt->drv_data.acc_data.values[1] ||
ACC_INVALID_VALUE == cxt->drv_data.acc_data.values[2])
{
ACC_LOG(" read invalid data \n");
goto acc_loop;
}
}
//report data to input device
//printk("new acc work run....\n");
//ACC_LOG("acc data[%d,%d,%d] \n" ,cxt->drv_data.acc_data.values[0],
//cxt->drv_data.acc_data.values[1],cxt->drv_data.acc_data.values[2]);
acc_data_report(cxt->drv_data.acc_data.values[0],
cxt->drv_data.acc_data.values[1],cxt->drv_data.acc_data.values[2],
cxt->drv_data.acc_data.status);
acc_loop:
if(true == cxt->is_polling_run)
{
mod_timer(&cxt->timer, jiffies + atomic_read(&cxt->delay)/(1000/HZ));
}
}
static void acc_poll(unsigned long data)
{
struct acc_context *obj = (struct acc_context *)data;
if(obj != NULL)
{
schedule_work(&obj->report);
}
}
static struct acc_context *acc_context_alloc_object(void)
{
struct acc_context *obj = kzalloc(sizeof(*obj), GFP_KERNEL);
ACC_LOG("acc_context_alloc_object++++\n");
if(!obj)
{
ACC_ERR("Alloc accel object error!\n");
return NULL;
}
atomic_set(&obj->delay, 200); /*5Hz*/// set work queue delay time 200ms
atomic_set(&obj->wake, 0);
INIT_WORK(&obj->report, acc_work_func);
init_timer(&obj->timer);
obj->timer.expires = jiffies + atomic_read(&obj->delay)/(1000/HZ);
obj->timer.function = acc_poll;
obj->timer.data = (unsigned long)obj;
obj->is_first_data_after_enable = false;
obj->is_polling_run = false;
mutex_init(&obj->acc_op_mutex);
obj->is_batch_enable = false;//for batch mode init
ACC_LOG("acc_context_alloc_object----\n");
return obj;
}
static int acc_real_enable(int enable)
{
int err =0;
struct acc_context *cxt = NULL;
cxt = acc_context_obj;
if(1==enable)
{
if(true==cxt->is_active_data || true ==cxt->is_active_nodata)
{
err = cxt->acc_ctl.enable_nodata(1);
if(err)
{
err = cxt->acc_ctl.enable_nodata(1);
if(err)
{
err = cxt->acc_ctl.enable_nodata(1);
if(err)
ACC_ERR("acc enable(%d) err 3 timers = %d\n", enable, err);
}
}
ACC_LOG("acc real enable \n" );
}
}
if(0==enable)
{
if(false==cxt->is_active_data && false ==cxt->is_active_nodata)
{
err = cxt->acc_ctl.enable_nodata(0);
if(err)
{
ACC_ERR("acc enable(%d) err = %d\n", enable, err);
}
ACC_LOG("acc real disable \n" );
}
}
return err;
}
static int acc_enable_data(int enable)
{
struct acc_context *cxt = NULL;
int err =0;
cxt = acc_context_obj;
if(NULL == cxt->acc_ctl.open_report_data)
{
ACC_ERR("no acc control path\n");
return -1;
}
if(1 == enable)
{
ACC_LOG("ACC enable data\n");
cxt->is_active_data =true;
cxt->is_first_data_after_enable = true;
cxt->acc_ctl.open_report_data(1);
if(false == cxt->is_polling_run && cxt->is_batch_enable == false)
{
if(false == cxt->acc_ctl.is_report_input_direct)
{
mod_timer(&cxt->timer, jiffies + atomic_read(&cxt->delay)/(1000/HZ));
cxt->is_polling_run = true;
}
}
}
if(0 == enable)
{
ACC_LOG("ACC disable \n");
cxt->is_active_data =false;
cxt->acc_ctl.open_report_data(0);
if(true == cxt->is_polling_run)
{
if(false == cxt->acc_ctl.is_report_input_direct)
{
cxt->is_polling_run = false;
del_timer_sync(&cxt->timer);
cancel_work_sync(&cxt->report);
cxt->drv_data.acc_data.values[0] = ACC_INVALID_VALUE;
cxt->drv_data.acc_data.values[1] = ACC_INVALID_VALUE;
cxt->drv_data.acc_data.values[2] = ACC_INVALID_VALUE;
}
}
}
acc_real_enable(enable);
return 0;
}
int acc_enable_nodata(int enable)
{
struct acc_context *cxt = NULL;
int err =0;
cxt = acc_context_obj;
if(NULL == cxt->acc_ctl.enable_nodata)
{
ACC_ERR("acc_enable_nodata:acc ctl path is NULL\n");
return -1;
}
if(1 == enable)
{
cxt->is_active_nodata = true;
}
if(0 == enable)
{
cxt->is_active_nodata = false;
}
acc_real_enable(enable);
return 0;
}
static ssize_t acc_show_enable_nodata(struct device* dev,
struct device_attribute *attr, char *buf)
{
int len = 0;
ACC_LOG(" not support now\n");
return len;
}
static ssize_t acc_store_enable_nodata(struct device* dev, struct device_attribute *attr,
const char *buf, size_t count)
{
ACC_LOG("acc_store_enable nodata buf=%s\n",buf);
mutex_lock(&acc_context_obj->acc_op_mutex);
struct acc_context *cxt = NULL;
int err =0;
cxt = acc_context_obj;
if(NULL == cxt->acc_ctl.enable_nodata)
{
ACC_LOG("acc_ctl enable nodata NULL\n");
mutex_unlock(&acc_context_obj->acc_op_mutex);
return count;
}
if (!strncmp(buf, "1", 1))
{
//cxt->acc_ctl.enable_nodata(1);
acc_enable_nodata(1);
}
else if (!strncmp(buf, "0", 1))
{
//cxt->acc_ctl.enable_nodata(0);
acc_enable_nodata(0);
}
else
{
ACC_ERR(" acc_store enable nodata cmd error !!\n");
}
mutex_unlock(&acc_context_obj->acc_op_mutex);
}
static ssize_t acc_store_active(struct device* dev, struct device_attribute *attr,
const char *buf, size_t count)
{
ACC_LOG("acc_store_active buf=%s\n",buf);
mutex_lock(&acc_context_obj->acc_op_mutex);
struct acc_context *cxt = NULL;
int err =0;
cxt = acc_context_obj;
if(NULL == cxt->acc_ctl.open_report_data)
{
ACC_LOG("acc_ctl enable NULL\n");
mutex_unlock(&acc_context_obj->acc_op_mutex);
return count;
}
if (!strncmp(buf, "1", 1))
{
// cxt->acc_ctl.enable(1);
acc_enable_data(1);
}
else if (!strncmp(buf, "0", 1))
{
//cxt->acc_ctl.enable(0);
acc_enable_data(0);
}
else
{
ACC_ERR(" acc_store_active error !!\n");
}
mutex_unlock(&acc_context_obj->acc_op_mutex);
ACC_LOG(" acc_store_active done\n");
return count;
}
/*----------------------------------------------------------------------------*/
static ssize_t acc_show_active(struct device* dev,
struct device_attribute *attr, char *buf)
{
struct acc_context *cxt = NULL;
cxt = acc_context_obj;
int div=cxt->acc_data.vender_div;
ACC_LOG("acc vender_div value: %d\n", div);
return snprintf(buf, PAGE_SIZE, "%d\n", div);
}
static ssize_t acc_store_delay(struct device* dev, struct device_attribute *attr,
const char *buf, size_t count)
{
mutex_lock(&acc_context_obj->acc_op_mutex);
struct acc_context *devobj = (struct acc_context*)dev_get_drvdata(dev);
int delay;
int mdelay=0;
struct acc_context *cxt = NULL;
int err =0;
cxt = acc_context_obj;
if(NULL == cxt->acc_ctl.set_delay)
{
ACC_LOG("acc_ctl set_delay NULL\n");
mutex_unlock(&acc_context_obj->acc_op_mutex);
return count;
}
if (1 != sscanf(buf, "%d", &delay)) {
ACC_ERR("invalid format!!\n");
mutex_unlock(&acc_context_obj->acc_op_mutex);
return count;
}
if(false == cxt->acc_ctl.is_report_input_direct)
{
mdelay = (int)delay/1000/1000;
atomic_set(&acc_context_obj->delay, mdelay);
}
cxt->acc_ctl.set_delay(delay);
ACC_LOG(" acc_delay %d ns\n",delay);
mutex_unlock(&acc_context_obj->acc_op_mutex);
return count;
}
static ssize_t acc_show_delay(struct device* dev,
struct device_attribute *attr, char *buf)
{
int len = 0;
ACC_LOG(" not support now\n");
return len;
}
static ssize_t acc_show_sensordevnum(struct device* dev,
struct device_attribute *attr, char *buf)
{
struct acc_context *cxt = NULL;
char *devname = NULL;
cxt = acc_context_obj;
devname = dev_name(&cxt->idev->dev);
return snprintf(buf, PAGE_SIZE, "%s\n", devname+5);
}
static ssize_t acc_store_batch(struct device* dev, struct device_attribute *attr,
const char *buf, size_t count)
{
ACC_LOG("acc_store_batch buf=%s\n",buf);
mutex_lock(&acc_context_obj->acc_op_mutex);
struct acc_context *cxt = NULL;
int err =0;
cxt = acc_context_obj;
if(cxt->acc_ctl.is_support_batch){
if (!strncmp(buf, "1", 1))
{
cxt->is_batch_enable = true;
}
else if (!strncmp(buf, "0", 1))
{
cxt->is_batch_enable = false;
}
else
{
ACC_ERR(" acc_store_batch error !!\n");
}
}else{
ACC_LOG(" acc_store_batch mot supported\n");
}
mutex_unlock(&acc_context_obj->acc_op_mutex);
ACC_LOG(" acc_store_batch done: %d\n", cxt->is_batch_enable);
return count;
}
static ssize_t acc_show_batch(struct device* dev,
struct device_attribute *attr, char *buf)
{
return snprintf(buf, PAGE_SIZE, "%d\n", 0);
}
static ssize_t acc_store_flush(struct device* dev, struct device_attribute *attr,
const char *buf, size_t count)
{
mutex_lock(&acc_context_obj->acc_op_mutex);
struct acc_context *devobj = (struct acc_context*)dev_get_drvdata(dev);
//do read FIFO data function and report data immediately
mutex_unlock(&acc_context_obj->acc_op_mutex);
return count;
}
static ssize_t acc_show_flush(struct device* dev,
struct device_attribute *attr, char *buf)
{
return snprintf(buf, PAGE_SIZE, "%d\n", 0);
}
static int gsensor_remove(struct platform_device *pdev)
{
ACC_LOG("gsensor_remove\n");
return 0;
}
static int gsensor_probe(struct platform_device *pdev)
{
ACC_LOG("gsensor_probe\n");
return 0;
}
static struct platform_driver gsensor_driver = {
.probe = gsensor_probe,
.remove = gsensor_remove,
.driver =
{
.name = "gsensor",
}
};
static int acc_real_driver_init(void)
{
int i =0;
int err=0;
ACC_LOG(" acc_real_driver_init +\n");
for(i = 0; i < MAX_CHOOSE_G_NUM; i++)
{
ACC_LOG(" i=%d\n",i);
if(0 != gsensor_init_list[i])
{
ACC_LOG(" acc try to init driver %s\n", gsensor_init_list[i]->name);
err = gsensor_init_list[i]->init();
if(0 == err)
{
ACC_LOG(" acc real driver %s probe ok\n", gsensor_init_list[i]->name);
break;
}
}
}
if(i == MAX_CHOOSE_G_NUM)
{
ACC_LOG(" acc_real_driver_init fail\n");
err=-1;
}
return err;
}
int acc_driver_add(struct acc_init_info* obj)
{
int err=0;
int i =0;
ACC_FUN();
for(i =0; i < MAX_CHOOSE_G_NUM; i++ )
{
if(i == 0){
ACC_LOG("register gensor driver for the first time\n");
if(platform_driver_register(&gsensor_driver))
{
ACC_ERR("failed to register gensor driver already exist\n");
}
}
if(NULL == gsensor_init_list[i])
{
obj->platform_diver_addr = &gsensor_driver;
gsensor_init_list[i] = obj;
break;
}
}
if(NULL==gsensor_init_list[i])
{
ACC_ERR("ACC driver add err \n");
err=-1;
}
return err;
}
EXPORT_SYMBOL_GPL(acc_driver_add);
static int acc_misc_init(struct acc_context *cxt)
{
int err=0;
cxt->mdev.minor = MISC_DYNAMIC_MINOR;
cxt->mdev.name = ACC_MISC_DEV_NAME;
if((err = misc_register(&cxt->mdev)))
{
ACC_ERR("unable to register acc misc device!!\n");
}
//dev_set_drvdata(cxt->mdev.this_device, cxt);
return err;
}
static void acc_input_destroy(struct acc_context *cxt)
{
struct input_dev *dev = cxt->idev;
input_unregister_device(dev);
input_free_device(dev);
}
static int acc_input_init(struct acc_context *cxt)
{
struct input_dev *dev;
int err = 0;
dev = input_allocate_device();
if (NULL == dev)
return -ENOMEM;
dev->name = ACC_INPUTDEV_NAME;
input_set_capability(dev, EV_ABS, EVENT_TYPE_ACCEL_X);
input_set_capability(dev, EV_ABS, EVENT_TYPE_ACCEL_Y);
input_set_capability(dev, EV_ABS, EVENT_TYPE_ACCEL_Z);
input_set_capability(dev, EV_ABS, EVENT_TYPE_ACCEL_STATUS);
input_set_abs_params(dev, EVENT_TYPE_ACCEL_X, ACC_VALUE_MIN, ACC_VALUE_MAX, 0, 0);
input_set_abs_params(dev, EVENT_TYPE_ACCEL_Y, ACC_VALUE_MIN, ACC_VALUE_MAX, 0, 0);
input_set_abs_params(dev, EVENT_TYPE_ACCEL_Z, ACC_VALUE_MIN, ACC_VALUE_MAX, 0, 0);
input_set_abs_params(dev, EVENT_TYPE_ACCEL_STATUS, ACC_STATUS_MIN, ACC_STATUS_MAX, 0, 0);
input_set_drvdata(dev, cxt);
err = input_register_device(dev);
if (err < 0) {
input_free_device(dev);
return err;
}
cxt->idev= dev;
return 0;
}
DEVICE_ATTR(accenablenodata, S_IWUSR | S_IRUGO, acc_show_enable_nodata, acc_store_enable_nodata);
DEVICE_ATTR(accactive, S_IWUSR | S_IRUGO, acc_show_active, acc_store_active);
DEVICE_ATTR(accdelay, S_IWUSR | S_IRUGO, acc_show_delay, acc_store_delay);
DEVICE_ATTR(accbatch, S_IWUSR | S_IRUGO, acc_show_batch, acc_store_batch);
DEVICE_ATTR(accflush, S_IWUSR | S_IRUGO, acc_show_flush, acc_store_flush);
DEVICE_ATTR(accdevnum, S_IWUSR | S_IRUGO, acc_show_sensordevnum, NULL);
static struct attribute *acc_attributes[] = {
&dev_attr_accenablenodata.attr,
&dev_attr_accactive.attr,
&dev_attr_accdelay.attr,
&dev_attr_accbatch.attr,
&dev_attr_accflush.attr,
&dev_attr_accdevnum.attr,
NULL
};
static struct attribute_group acc_attribute_group = {
.attrs = acc_attributes
};
int acc_register_data_path(struct acc_data_path *data)
{
struct acc_context *cxt = NULL;
int err =0;
cxt = acc_context_obj;
cxt->acc_data.get_data = data->get_data;
cxt->acc_data.vender_div = data->vender_div;
ACC_LOG("acc register data path vender_div: %d\n", cxt->acc_data.vender_div);
if(NULL == cxt->acc_data.get_data)
{
ACC_LOG("acc register data path fail \n");
return -1;
}
return 0;
}
int acc_register_control_path(struct acc_control_path *ctl)
{
struct acc_context *cxt = NULL;
int err =0;
cxt = acc_context_obj;
cxt->acc_ctl.set_delay = ctl->set_delay;
cxt->acc_ctl.open_report_data= ctl->open_report_data;
cxt->acc_ctl.enable_nodata = ctl->enable_nodata;
cxt->acc_ctl.is_support_batch = ctl->is_support_batch;
cxt->acc_ctl.is_report_input_direct= ctl->is_report_input_direct;
if(NULL==cxt->acc_ctl.set_delay || NULL==cxt->acc_ctl.open_report_data
|| NULL==cxt->acc_ctl.enable_nodata)
{
ACC_LOG("acc register control path fail \n");
return -1;
}
//add misc dev for sensor hal control cmd
err = acc_misc_init(acc_context_obj);
if(err)
{
ACC_ERR("unable to register acc misc device!!\n");
return -2;
}
err = sysfs_create_group(&acc_context_obj->mdev.this_device->kobj,
&acc_attribute_group);
if (err < 0)
{
ACC_ERR("unable to create acc attribute file\n");
return -3;
}
kobject_uevent(&acc_context_obj->mdev.this_device->kobj, KOBJ_ADD);
return 0;
}
int acc_data_report(int x, int y, int z,int status)
{
//ACC_LOG("+acc_data_report! %d, %d, %d, %d\n",x,y,z,status);
struct acc_context *cxt = NULL;
int err =0;
cxt = acc_context_obj;
input_report_abs(cxt->idev, EVENT_TYPE_ACCEL_X, x);
input_report_abs(cxt->idev, EVENT_TYPE_ACCEL_Y, y);
input_report_abs(cxt->idev, EVENT_TYPE_ACCEL_Z, z);
input_report_abs(cxt->idev, EVENT_TYPE_ACCEL_STATUS, status);
input_sync(cxt->idev);
}
static int acc_probe(struct platform_device *pdev)
{
int err;
ACC_LOG("+++++++++++++accel_probe!!\n");
acc_context_obj = acc_context_alloc_object();
if (!acc_context_obj)
{
err = -ENOMEM;
ACC_ERR("unable to allocate devobj!\n");
goto exit_alloc_data_failed;
}
//init real acceleration driver
err = acc_real_driver_init();
if(err)
{
ACC_ERR("acc real driver init fail\n");
goto real_driver_init_fail;
}
//init input dev
err = acc_input_init(acc_context_obj);
if(err)
{
ACC_ERR("unable to register acc input device!\n");
goto exit_alloc_input_dev_failed;
}
atomic_set(&(acc_context_obj->early_suspend), 0);
acc_context_obj->early_drv.level = EARLY_SUSPEND_LEVEL_STOP_DRAWING - 1,
acc_context_obj->early_drv.suspend = acc_early_suspend,
acc_context_obj->early_drv.resume = acc_late_resume,
register_early_suspend(&acc_context_obj->early_drv);
ACC_LOG("----accel_probe OK !!\n");
return 0;
exit_hwmsen_create_attr_failed:
exit_misc_register_failed:
exit_err_sysfs:
if (err)
{
ACC_ERR("sysfs node creation error \n");
acc_input_destroy(acc_context_obj);
}
real_driver_init_fail:
exit_alloc_input_dev_failed:
kfree(acc_context_obj);
exit_alloc_data_failed:
ACC_LOG("----accel_probe fail !!!\n");
return err;
}
static int acc_remove(struct platform_device *pdev)
{
ACC_FUN(f);
int err=0;
input_unregister_device(acc_context_obj->idev);
sysfs_remove_group(&acc_context_obj->idev->dev.kobj,
&acc_attribute_group);
if((err = misc_deregister(&acc_context_obj->mdev)))
{
ACC_ERR("misc_deregister fail: %d\n", err);
}
kfree(acc_context_obj);
return 0;
}
static void acc_early_suspend(struct early_suspend *h)
{
atomic_set(&(acc_context_obj->early_suspend), 1);
ACC_LOG(" acc_early_suspend ok------->hwm_obj->early_suspend=%d \n",atomic_read(&(acc_context_obj->early_suspend)));
return ;
}
/*----------------------------------------------------------------------------*/
static void acc_late_resume(struct early_suspend *h)
{
atomic_set(&(acc_context_obj->early_suspend), 0);
ACC_LOG(" acc_late_resume ok------->hwm_obj->early_suspend=%d \n",atomic_read(&(acc_context_obj->early_suspend)));
return ;
}
static int acc_suspend(struct platform_device *dev, pm_message_t state)
{
return 0;
}
/*----------------------------------------------------------------------------*/
static int acc_resume(struct platform_device *dev)
{
return 0;
}
static struct platform_driver acc_driver =
{
.probe = acc_probe,
.remove = acc_remove,
.suspend = acc_suspend,
.resume = acc_resume,
.driver =
{
.name = ACC_PL_DEV_NAME,
}
};
static int __init acc_init(void)
{
ACC_FUN();
if(platform_driver_register(&acc_driver))
{
ACC_ERR("failed to register acc driver\n");
return -ENODEV;
}
return 0;
}
static void __exit acc_exit(void)
{
platform_driver_unregister(&acc_driver);
platform_driver_unregister(&gsensor_driver);
}
module_init(acc_init);
module_exit(acc_exit);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("ACCELEROMETER device driver");
MODULE_AUTHOR("Mediatek");
arch/arm/mach-mt8127/ford/accelerometer/accel.h
+123
View File
@@ -0,0 +1,123 @@
#ifndef __ACC_H__
#define __ACC_H__
#include <linux/wakelock.h>
#include <linux/interrupt.h>
#include <linux/miscdevice.h>
#include <linux/platform_device.h>
#include <linux/input.h>
#include <linux/workqueue.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/hwmsensor.h>
#include <linux/earlysuspend.h>
#include <linux/hwmsen_dev.h>
#define ACC_TAG "<ACCELEROMETER> "
#define ACC_FUN(f) printk(KERN_ERR ACC_TAG"%s\n", __func__)
#define ACC_ERR(fmt, args...) printk(KERN_ERR ACC_TAG"%s %d : "fmt, __func__, __LINE__, ##args)
#define ACC_LOG(fmt, args...) printk(KERN_ERR ACC_TAG fmt, ##args)
#define ACC_VER(fmt, args...) printk(KERN_ERR ACC_TAG"%s: "fmt, __func__, ##args) //((void)0)
#define OP_ACC_DELAY 0X01
#define OP_ACC_ENABLE 0X02
#define OP_ACC_GET_DATA 0X04
#define ACC_INVALID_VALUE -1
#define EVENT_TYPE_ACCEL_X ABS_X
#define EVENT_TYPE_ACCEL_Y ABS_Y
#define EVENT_TYPE_ACCEL_Z ABS_Z
#define EVENT_TYPE_ACCEL_STATUS ABS_WHEEL
#define EVENT_TYPE_ACCEL_DIV ABS_GAS
#define ACC_VALUE_MAX (32767)
#define ACC_VALUE_MIN (-32768)
#define ACC_STATUS_MIN (0)
#define ACC_STATUS_MAX (64)
#define ACC_DIV_MAX (32767)
#define ACC_DIV_MIN (1)
#define MAX_CHOOSE_G_NUM 5
struct acc_control_path
{
int (*open_report_data)(int open);//open data rerport to HAL
int (*enable_nodata)(int en);//only enable not report event to HAL
int (*set_delay)(u64 delay);
int (*access_data_fifo)();//version2.used for flush operate
bool is_report_input_direct;
bool is_support_batch;//version2.used for batch mode support flag
};
struct acc_data_path
{
int (*get_data)(int *x,int *y, int *z,int *status);
int vender_div;
};
struct acc_init_info
{
char *name;
int (*init)(void);
int (*uninit)(void);
struct platform_driver* platform_diver_addr;
};
struct acc_data{
hwm_sensor_data acc_data ;
int data_updata;
//struct mutex lock;
};
struct acc_drv_obj {
void *self;
int polling;
int (*acc_operate)(void* self, uint32_t command, void* buff_in, int size_in,
void* buff_out, int size_out, int* actualout);
};
struct acc_context {
struct input_dev *idev;
struct miscdevice mdev;
struct work_struct report;
struct mutex acc_op_mutex;
atomic_t delay; /*polling period for reporting input event*/
atomic_t wake; /*user-space request to wake-up, used with stop*/
struct timer_list timer; /* polling timer */
atomic_t trace;
struct early_suspend early_drv;
atomic_t early_suspend;
//struct acc_drv_obj drv_obj;
struct acc_data drv_data;
struct acc_control_path acc_ctl;
struct acc_data_path acc_data;
bool is_active_nodata; // Active, but HAL don't need data sensor. such as orientation need
bool is_active_data; // Active and HAL need data .
bool is_first_data_after_enable;
bool is_polling_run;
bool is_batch_enable; //version2.this is used for judging whether sensor is in batch mode
};
//driver API for internal
//extern int acc_enable_nodata(int enable);
//extern int acc_attach(struct acc_drv_obj *obj);
//driver API for third party vendor
//for auto detect
extern int acc_driver_add(struct acc_init_info* obj) ;
extern int acc_data_report(int x, int y, int z,int status);
extern int acc_register_control_path(struct acc_control_path *ctl);
extern int acc_register_data_path(struct acc_data_path *data);
#endif
arch/arm/mach-mt8127/ford/accelerometer/cust_acc.c
+18
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@@ -0,0 +1,18 @@
#include <linux/types.h>
#include <cust_acc.h>
#include <mach/mt_pm_ldo.h>
/*---------------------------------------------------------------------------*/
static struct acc_hw cust_acc_hw = {
.i2c_num = 2,
.direction = 7,
.power_id = MT65XX_POWER_NONE, /*!< LDO is not used */
.power_vol= VOL_DEFAULT, /*!< LDO is not used */
.firlen = 0, //old value 16 /*!< don't enable low pass fileter */
};
/*---------------------------------------------------------------------------*/
struct acc_hw* get_cust_acc_hw(void)
{
return &cust_acc_hw;
}
arch/arm/mach-mt8127/ford/accelerometer/inc/cust_acc.h
+22
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@@ -0,0 +1,22 @@
#ifndef __CUST_ACC_H__
#define __CUST_ACC_H__
#include <linux/types.h>
#define G_CUST_I2C_ADDR_NUM 2
struct acc_hw {
int i2c_num; /*!< the i2c bus used by the chip */
int direction; /*!< the direction of the chip */
int power_id; /*!< the VDD LDO ID of the chip, MT6516_POWER_NONE means the power is always on*/
int power_vol; /*!< the VDD Power Voltage used by the chip */
int firlen; /*!< the length of low pass filter */
int (*power)(struct acc_hw *hw, unsigned int on, char *devname);
unsigned char i2c_addr[G_CUST_I2C_ADDR_NUM]; /*!< i2c address list,for chips which has different addresses with different HW layout */
int power_vio_id; /*!< the VIO LDO ID of the chip, MT6516_POWER_NONE means the power is always on*/
int power_vio_vol; /*!< the VIO Power Voltage used by the chip */
bool is_batch_supported;
};
extern struct acc_hw* get_cust_acc_hw(void);
#endif
arch/arm/mach-mt8127/ford/accelerometer/mpu6050.c
+2249
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arch/arm/mach-mt8127/ford/accelerometer/mpu6050.h
+60
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@@ -0,0 +1,60 @@
#ifndef MPU6050_H
#define MPU6050_H
#include <linux/ioctl.h>
#define MPU6050_I2C_SLAVE_ADDR 0xD0
/* MPU6050 Register Map (Please refer to MPU6050 Specifications) */
#define MPU6050_REG_DEVID 0x75
#define MPU6050_REG_BW_RATE 0x1A
#define MPU6050_REG_POWER_CTL 0x6B
#define MPU6050_REG_POWER_CTL2 0x6C
#define MPU6050_REG_INT_ENABLE 0x38
#define MPU6050_REG_DATA_FORMAT 0x1C
#define MPU6050_REG_DATAX0 0x3B
#define MPU6050_REG_DATAY0 0x3D
#define MPU6050_REG_DATAZ0 0x3F
#define MPU6050_REG_RESET 0x68
/* register Value */
#define MPU6050_FIXED_DEVID 0x68 // or 0x69
// delay(ms)
#define MPU6050_BW_260HZ 0x00 //0
#define MPU6050_BW_184HZ 0x01 //2.0
#define MPU6050_BW_94HZ 0x02 //3.0
#define MPU6050_BW_44HZ 0x03 //4.9
#define MPU6050_BW_21HZ 0x04 //8.5
#define MPU6050_BW_10HZ 0x05 //13.8
#define MPU6050_BW_5HZ 0x06 //19.0
#define MPU6050_DEV_RESET 0x80
//#define MPU6050_FULL_RES 0x08
#define MPU6050_RANGE_2G (0x00 << 3)
#define MPU6050_RANGE_4G (0x01 << 3)
#define MPU6050_RANGE_8G (0x02 << 3)
#define MPU6050_RANGE_16G (0x03 << 3)
//#define MPU6050_SELF_TEST 0x80
#define MPU6050_SLEEP 0x40 //enable low power sleep mode
// below do not modify
#define MPU6050_SUCCESS 0
#define MPU6050_ERR_I2C -1
#define MPU6050_ERR_STATUS -3
#define MPU6050_ERR_SETUP_FAILURE -4
#define MPU6050_ERR_GETGSENSORDATA -5
#define MPU6050_ERR_IDENTIFICATION -6
#define MPU6050_BUFSIZE 256
#endif
arch/arm/mach-mt8127/ford/alsps/APDS9930.c
+1990
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arch/arm/mach-mt8127/ford/alsps/APDS9930.h
+60
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@@ -0,0 +1,60 @@
/*
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
/*
* Definitions for APDS9930 als/ps sensor chip.
*/
#ifndef __APDS9930_H__
#define __APDS9930_H__
#include <linux/ioctl.h>
extern int APDS9930_CMM_PPCOUNT_VALUE;
extern int APDS9930_CMM_CONTROL_VALUE;
extern int ZOOM_TIME;
#define APDS9930_CMM_ENABLE 0X80
#define APDS9930_CMM_ATIME 0X81
#define APDS9930_CMM_PTIME 0X82
#define APDS9930_CMM_WTIME 0X83
/*for interrup work mode support -- by liaoxl.lenovo 12.08.2011*/
#define APDS9930_CMM_INT_LOW_THD_LOW 0X88
#define APDS9930_CMM_INT_LOW_THD_HIGH 0X89
#define APDS9930_CMM_INT_HIGH_THD_LOW 0X8A
#define APDS9930_CMM_INT_HIGH_THD_HIGH 0X8B
#define APDS9930_CMM_Persistence 0X8C
#define APDS9930_CMM_STATUS 0X93
#define TAOS_TRITON_CMD_REG 0X80
#define TAOS_TRITON_CMD_SPL_FN 0x60
#define APDS9930_CMM_CONFIG 0X8D
#define APDS9930_CMM_PPCOUNT 0X8E
#define APDS9930_CMM_CONTROL 0X8F
#define APDS9930_CMM_PDATA_L 0X98
#define APDS9930_CMM_PDATA_H 0X99
#define APDS9930_CMM_C0DATA_L 0X94
#define APDS9930_CMM_C0DATA_H 0X95
#define APDS9930_CMM_C1DATA_L 0X96
#define APDS9930_CMM_C1DATA_H 0X97
#define APDS9930_SUCCESS 0
#define APDS9930_ERR_I2C -1
#define APDS9930_ERR_STATUS -3
#define APDS9930_ERR_SETUP_FAILURE -4
#define APDS9930_ERR_GETGSENSORDATA -5
#define APDS9930_ERR_IDENTIFICATION -6
#endif
drivers/misc/mediatek/imgsensor/src/mt8127/gc2355_raw/Makefile → arch/arm/mach-mt8127/ford/alsps/Makefile
Regular → Executable
+1 -1
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@@ -1,4 +1,4 @@
include $(srctree)/drivers/misc/mediatek/Makefile.custom
obj-y += gc2355_Sensor.o
obj-y += cust_alsps.o
arch/arm/mach-mt8127/ford/alsps/alsps.c
+1094
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arch/arm/mach-mt8127/ford/alsps/alsps.h
+153
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@@ -0,0 +1,153 @@
#ifndef __ALSPS_H__
#define __ALSPS_H__
#include <linux/wakelock.h>
#include <linux/interrupt.h>
#include <linux/miscdevice.h>
#include <linux/platform_device.h>
#include <linux/input.h>
#include <linux/workqueue.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/hwmsensor.h>
#include <linux/earlysuspend.h>
#include <linux/hwmsen_dev.h>
#define ALSPS_TAG "<ALS/PS> "
#define ALSPS_FUN(f) printk(ALSPS_TAG"%s\n", __func__)
#define ALSPS_ERR(fmt, args...) printk(ALSPS_TAG"%s %d : "fmt, __func__, __LINE__, ##args)
#define ALSPS_LOG(fmt, args...) printk(ALSPS_TAG fmt, ##args)
#define ALSPS_VER(fmt, args...) printk(ALSPS_TAG"%s: "fmt, __func__, ##args) //((void)0)
#define OP_ALSPS_DELAY 0X01
#define OP_ALSPS_ENABLE 0X02
#define OP_ALSPS_GET_DATA 0X04
#define ALSPS_INVALID_VALUE -1
#define EVENT_TYPE_ALS_VALUE ABS_X
#define EVENT_TYPE_PS_VALUE ABS_Z
#define EVENT_TYPE_ALS_STATUS ABS_WHEEL
#define EVENT_TYPE_PS_STATUS ABS_Y
#define ALSPS_VALUE_MAX (32767)
#define ALSPS_VALUE_MIN (-32768)
#define ALSPS_STATUS_MIN (0)
#define ALSPS_STATUS_MAX (64)
#define ALSPS_DIV_MAX (32767)
#define ALSPS_DIV_MIN (1)
#define MAX_CHOOSE_ALSPS_NUM 5
struct als_control_path
{
int (*open_report_data)(int open);//open data rerport to HAL
int (*enable_nodata)(int en);//only enable not report event to HAL
int (*set_delay)(u64 delay);
int (*access_data_fifo)();//version2.used for flush operate
bool is_report_input_direct;
bool is_support_batch;//version2.used for batch mode support flag
bool is_polling_mode;
};
struct ps_control_path
{
int (*open_report_data)(int open);//open data rerport to HAL
int (*enable_nodata)(int en);//only enable not report event to HAL
int (*set_delay)(u64 delay);
int (*access_data_fifo)();//version2.used for flush operate
bool is_report_input_direct;
bool is_support_batch;//version2.used for batch mode support flag
bool is_polling_mode;
};
struct als_data_path
{
int (*get_data)(int *als_value, int *status);
int vender_div;
};
struct ps_data_path
{
int (*get_data)(int *ps_value, int *status);
int vender_div;
};
struct alsps_init_info
{
char *name;
int (*init)(void);
int (*uninit)(void);
struct platform_driver* platform_diver_addr;
};
struct alsps_data{
hwm_sensor_data als_data ;
hwm_sensor_data ps_data ;
int data_updata;
};
struct alsps_drv_obj {
void *self;
int polling;
int (*alsps_operate)(void* self, uint32_t command, void* buff_in, int size_in,
void* buff_out, int size_out, int* actualout);
};
struct alsps_context {
struct input_dev *idev;
struct miscdevice mdev;
struct work_struct report_ps;
struct work_struct report_als;
struct mutex alsps_op_mutex;
struct timer_list timer_als; /*als polling timer */
struct timer_list timer_ps; /* ps polling timer */
atomic_t trace;
atomic_t delay_als; /*als polling period for reporting input event*/
atomic_t delay_ps;/*ps polling period for reporting input event*/
atomic_t wake; /*user-space request to wake-up, used with stop*/
struct early_suspend early_drv;
atomic_t early_suspend;
struct alsps_data drv_data;
struct als_control_path als_ctl;
struct als_data_path als_data;
struct ps_control_path ps_ctl;
struct ps_data_path ps_data;
bool is_als_active_nodata;// Active, but HAL don't need data sensor. such as orientation need
bool is_als_active_data;// Active and HAL need data .
bool is_ps_active_nodata;// Active, but HAL don't need data sensor. such as orientation need
bool is_ps_active_data;// Active and HAL need data .
bool is_als_first_data_after_enable;
bool is_ps_first_data_after_enable;
bool is_als_polling_run;
bool is_ps_polling_run;
bool is_als_batch_enable; //version2.this is used for judging whether sensor is in batch mode
bool is_ps_batch_enable; //version2.this is used for judging whether sensor is in batch mode
};
//for auto detect
extern int alsps_driver_add(struct alsps_init_info* obj) ;
extern int ps_report_interrupt_data(int value);
extern int als_data_report(struct input_dev *dev, int value,int status);
extern int als_register_control_path(struct als_control_path *ctl);
extern int als_register_data_path(struct als_data_path *data);
extern int ps_data_report(struct input_dev *dev, int value,int status);
extern int ps_register_control_path(struct ps_control_path *ctl);
extern int ps_register_data_path(struct ps_data_path *data);
#endif
arch/arm/mach-mt8127/ford/alsps/cust_alsps.c
+27
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@@ -0,0 +1,27 @@
#include <linux/types.h>
#include <mach/mt_pm_ldo.h>
#include <cust_alsps.h>
//#include <mach/mt6577_pm_ldo.h>
static struct alsps_hw cust_alsps_hw = {
.i2c_num = 2,
.polling_mode_ps =0,
.polling_mode_als =1,
.power_id = MT65XX_POWER_NONE, /*LDO is not used*/
.power_vol = VOL_DEFAULT, /*LDO is not used*/
.i2c_addr = {0x72, 0x48, 0x78, 0x00},
/*Lenovo-sw chenlj2 add 2011-06-03,modify parameter below two lines*/
//.als_level = { 4, 40, 80, 120, 160, 250, 400, 800, 1200, 1600, 2000, 3000, 5000, 10000, 65535},
//.als_value = {10, 20,20, 120, 120, 280, 280, 280, 1600, 1600, 1600, 6000, 6000, 9000, 10240, 10240},
.als_level = { 5, 10, 25, 50, 100, 150, 200, 400, 1000, 1500, 2000, 3000, 5000, 8000, 10000},
.als_value = {10, 50, 100, 150, 200, 250, 280, 280, 1600, 1600, 1600, 6000, 6000, 9000, 10240, 10240},
.ps_threshold_high = 120,
.ps_threshold_low = 100,
.ps_threshold = 900,
};
struct alsps_hw *get_cust_alsps_hw(void) {
return &cust_alsps_hw;
}
int APDS9930_CMM_PPCOUNT_VALUE = 0x08;
int APDS9930_CMM_CONTROL_VALUE = 0xE4;
int ZOOM_TIME = 4;
arch/arm/mach-mt8127/ford/alsps/inc/cust_alsps.h
+42
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@@ -0,0 +1,42 @@
#ifndef __CUST_ALSPS_H__
#define __CUST_ALSPS_H__
#include <linux/types.h>
#define C_CUST_ALS_LEVEL 16
#define C_CUST_I2C_ADDR_NUM 4
#define MAX_THRESHOLD_HIGH 0xffff
#define MIN_THRESHOLD_LOW 0x0
struct alsps_hw {
int i2c_num; /*!< the i2c bus used by ALS/PS */
int power_id; /*!< the VDD power id of the als chip */
int power_vol; /*!< the VDD power voltage of the als chip */
int polling_mode; /*!< 1: polling mode ; 0:interrupt mode*/
int polling_mode_ps; /*!< 1: polling mode ; 0:interrupt mode*/
int polling_mode_als; /*!< 1: polling mode ; 0:interrupt mode*/
unsigned char i2c_addr[C_CUST_I2C_ADDR_NUM]; /*!< i2c address list, some chip will have multiple address */
unsigned int als_level[C_CUST_ALS_LEVEL-1]; /*!< (C_CUST_ALS_LEVEL-1) levels divides all range into C_CUST_ALS_LEVEL levels*/
unsigned int als_value[C_CUST_ALS_LEVEL]; /*!< the value reported in each level */
unsigned int ps_threshold; /*!< the threshold of proximity sensor */
unsigned int als_window_loss; /*!< the window loss */
unsigned int ps_threshold_high;
unsigned int ps_threshold_low;
unsigned int als_threshold_high;
unsigned int als_threshold_low;
int als_power_vio_id; /*!< the VIO power id of the als chip */
int als_power_vio_vol; /*!< the VIO power voltage of the als chip */
int ps_power_vdd_id; /*!< the VDD power id of the ps chip */
int ps_power_vdd_vol; /*!< the VDD power voltage of the ps chip */
int ps_power_vio_id; /*!< the VIO power id of the ps chip */
int ps_power_vio_vol; /*!< the VIO power voltage of the ps chip */
int power_lp_mode_ctrl; /*!< 1: disable ldo low power mode when p sensor enabled ; 0: no action*/
bool is_batch_supported_ps;
bool is_batch_supported_als;
};
extern struct alsps_hw* get_cust_alsps_hw(void);
__weak int pmic_ldo_suspend_enable(int enable);
#endif
arch/arm/mach-mt8127/ford/cam_cal/Makefile
Executable
+3
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@@ -0,0 +1,3 @@
include $(srctree)/drivers/misc/mediatek/Makefile.custom
obj-y := dummy_cam_cal.o
arch/arm/mach-mt8127/ford/cam_cal/dummy_cam_cal.c
+647
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@@ -0,0 +1,647 @@
/*
* Driver for CAM_CAL
*
*
*/
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/cdev.h>
#include <linux/uaccess.h>
#include <linux/slab.h>
#include <linux/fs.h>
#include "kd_camera_hw.h"
#include "cam_cal.h"
#include "cam_cal_define.h"
#include "dummy_cam_cal.h"
#include <asm/system.h> // for SMP
//#define CAM_CALGETDLT_DEBUG //test
//#define CAM_CAL_DEBUG //test
#ifdef CAM_CAL_DEBUG
#define CAM_CALDB printk
#else
#define CAM_CALDB(x,...)
#endif
static DEFINE_SPINLOCK(g_CAM_CALLock); // for SMP
#define CAM_CAL_I2C_BUSNUM 1
static struct i2c_board_info __initdata kd_cam_cal_dev={ I2C_BOARD_INFO("dummy_cam_cal", 0xAB>>1)}; //make dummy_eeprom co-exist
/*******************************************************************************
*
********************************************************************************/
#define CAM_CAL_ICS_REVISION 1 //seanlin111208
/*******************************************************************************
*
********************************************************************************/
#define CAM_CAL_DRVNAME "dummy_cam_cal"
#define CAM_CAL_I2C_GROUP_ID 0
/*******************************************************************************
*
********************************************************************************/
/* fix warning MSG
static unsigned short g_pu2Normal_i2c[] = {S24CS64A_DEVICE_ID , I2C_CLIENT_END};
static unsigned short g_u2Ignore = I2C_CLIENT_END;
static struct i2c_client_address_data g_stCAM_CAL_Addr_data = {
.normal_i2c = g_pu2Normal_i2c,
.probe = &g_u2Ignore,
.ignore = &g_u2Ignore
}; */
static struct i2c_client * g_pstI2Cclient = NULL;
//81 is used for V4L driver
static dev_t g_CAM_CALdevno = MKDEV(CAM_CAL_DEV_MAJOR_NUMBER,0);
static struct cdev * g_pCAM_CAL_CharDrv = NULL;
//static spinlock_t g_CAM_CALLock;
static struct class *CAM_CAL_class = NULL;
static atomic_t g_CAM_CALatomic;
/*******************************************************************************
*
********************************************************************************/
// maximun read length is limited at "I2C_FIFO_SIZE" in I2c-mt65xx.c which is 8 bytes
int iWriteCAM_CAL(u16 a_u2Addr , u32 a_u4Bytes, u8 * puDataInBytes)
{
int i4RetValue = 0;
u32 u4Index = 0;
char puSendCmd[8] = {(char)(a_u2Addr >> 8) , (char)(a_u2Addr & 0xFF) ,
0, 0, 0, 0, 0, 0};
if(a_u4Bytes + 2 > 8)
{
CAM_CALDB("[CAM_CAL] exceed I2c-mt65xx.c 8 bytes limitation (include address 2 Byte)\n");
return -1;
}
for(u4Index = 0 ; u4Index < a_u4Bytes ; u4Index += 1 )
{
puSendCmd[(u4Index + 2)] = puDataInBytes[u4Index];
}
i4RetValue = i2c_master_send(g_pstI2Cclient, puSendCmd, (a_u4Bytes + 2));
if (i4RetValue != (a_u4Bytes + 2))
{
CAM_CALDB("[CAM_CAL] I2C write failed!! \n");
return -1;
}
mdelay(10); //for tWR singnal --> write data form buffer to memory.
//CAM_CALDB("[CAM_CAL] iWriteCAM_CAL done!! \n");
return 0;
}
// maximun read length is limited at "I2C_FIFO_SIZE" in I2c-mt65xx.c which is 8 bytes
int iReadCAM_CAL(u16 a_u2Addr, u32 ui4_length, u8 * a_puBuff)
{
int i4RetValue = 0;
char puReadCmd[2] = {(char)(a_u2Addr >> 8) , (char)(a_u2Addr & 0xFF)};
//CAM_CALDB("[CAM_CAL] iReadCAM_CAL!! \n");
if(ui4_length > 8)
{
CAM_CALDB("[CAM_CAL] exceed I2c-mt65xx.c 8 bytes limitation\n");
return -1;
}
spin_lock(&g_CAM_CALLock); //for SMP
g_pstI2Cclient->addr = g_pstI2Cclient->addr & (I2C_MASK_FLAG | I2C_WR_FLAG);
spin_unlock(&g_CAM_CALLock); // for SMP
//CAM_CALDB("[EERPOM] i2c_master_send \n");
i4RetValue = i2c_master_send(g_pstI2Cclient, puReadCmd, 2);
if (i4RetValue != 2)
{
CAM_CALDB("[CAM_CAL] I2C send read address failed!! \n");
return -1;
}
//CAM_CALDB("[EERPOM] i2c_master_recv \n");
i4RetValue = i2c_master_recv(g_pstI2Cclient, (char *)a_puBuff, ui4_length);
if (i4RetValue != ui4_length)
{
CAM_CALDB("[CAM_CAL] I2C read data failed!! \n");
return -1;
}
spin_lock(&g_CAM_CALLock); //for SMP
g_pstI2Cclient->addr = g_pstI2Cclient->addr & I2C_MASK_FLAG;
spin_unlock(&g_CAM_CALLock); // for SMP
//CAM_CALDB("[CAM_CAL] iReadCAM_CAL done!! \n");
return 0;
}
static int iWriteData(unsigned int ui4_offset, unsigned int ui4_length, unsigned char * pinputdata)
{
int i4RetValue = 0;
int i4ResidueDataLength;
u32 u4IncOffset = 0;
u32 u4CurrentOffset;
u8 * pBuff;
CAM_CALDB("[CAM_CAL] iWriteData\n" );
if (ui4_offset + ui4_length >= 0x2000)
{
CAM_CALDB("[CAM_CAL] Write Error!! S-24CS64A not supprt address >= 0x2000!! \n" );
return -1;
}
i4ResidueDataLength = (int)ui4_length;
u4CurrentOffset = ui4_offset;
pBuff = pinputdata;
CAM_CALDB("[CAM_CAL] iWriteData u4CurrentOffset is %d \n",u4CurrentOffset);
do
{
if(i4ResidueDataLength >= 6)
{
i4RetValue = iWriteCAM_CAL((u16)u4CurrentOffset, 6, pBuff);
if (i4RetValue != 0)
{
CAM_CALDB("[CAM_CAL] I2C iWriteData failed!! \n");
return -1;
}
u4IncOffset += 6;
i4ResidueDataLength -= 6;
u4CurrentOffset = ui4_offset + u4IncOffset;
pBuff = pinputdata + u4IncOffset;
}
else
{
i4RetValue = iWriteCAM_CAL((u16)u4CurrentOffset, i4ResidueDataLength, pBuff);
if (i4RetValue != 0)
{
CAM_CALDB("[CAM_CAL] I2C iWriteData failed!! \n");
return -1;
}
u4IncOffset += 6;
i4ResidueDataLength -= 6;
u4CurrentOffset = ui4_offset + u4IncOffset;
pBuff = pinputdata + u4IncOffset;
//break;
}
}while (i4ResidueDataLength > 0);
CAM_CALDB("[CAM_CAL] iWriteData done\n" );
return 0;
}
//int iReadData(stCAM_CAL_INFO_STRUCT * st_pOutputBuffer)
static int iReadData(unsigned int ui4_offset, unsigned int ui4_length, unsigned char * pinputdata)
{
int i4RetValue = 0;
int i4ResidueDataLength;
u32 u4IncOffset = 0;
u32 u4CurrentOffset;
u8 * pBuff;
CAM_CALDB("[CAM_CAL] iReadData \n" );
if (ui4_offset + ui4_length >= 0x2000)
{
CAM_CALDB("[CAM_CAL] Read Error!! S-24CS64A not supprt address >= 0x2000!! \n" );
return -1;
}
i4ResidueDataLength = (int)ui4_length;
u4CurrentOffset = ui4_offset;
pBuff = pinputdata;
do
{
if(i4ResidueDataLength >= 8)
{
i4RetValue = iReadCAM_CAL((u16)u4CurrentOffset, 8, pBuff);
if (i4RetValue != 0)
{
CAM_CALDB("[CAM_CAL] I2C iReadData failed!! \n");
return -1;
}
u4IncOffset += 8;
i4ResidueDataLength -= 8;
u4CurrentOffset = ui4_offset + u4IncOffset;
pBuff = pinputdata + u4IncOffset;
}
else
{
i4RetValue = iReadCAM_CAL((u16)u4CurrentOffset, i4ResidueDataLength, pBuff);
if (i4RetValue != 0)
{
CAM_CALDB("[CAM_CAL] I2C iReadData failed!! \n");
return -1;
}
u4IncOffset += 8;
i4ResidueDataLength -= 8;
u4CurrentOffset = ui4_offset + u4IncOffset;
pBuff = pinputdata + u4IncOffset;
//break;
}
}while (i4ResidueDataLength > 0);
//fix warning MSG CAM_CALDB("[CAM_CAL] iReadData finial address is %d length is %d buffer address is 0x%x\n",u4CurrentOffset, i4ResidueDataLength, pBuff);
CAM_CALDB("[CAM_CAL] iReadData done\n" );
return 0;
}
/*******************************************************************************
*
********************************************************************************/
#define NEW_UNLOCK_IOCTL
#ifndef NEW_UNLOCK_IOCTL
static int CAM_CAL_Ioctl(struct inode * a_pstInode,
struct file * a_pstFile,
unsigned int a_u4Command,
unsigned long a_u4Param)
#else
static long CAM_CAL_Ioctl(
struct file *file,
unsigned int a_u4Command,
unsigned long a_u4Param
)
#endif
{
int i4RetValue = 0;
u8 * pBuff = NULL;
u8 * pWorkingBuff = NULL;
stCAM_CAL_INFO_STRUCT *ptempbuf;
#ifdef CAM_CALGETDLT_DEBUG
struct timeval ktv1, ktv2;
unsigned long TimeIntervalUS;
#endif
if(_IOC_NONE == _IOC_DIR(a_u4Command))
{
}
else
{
pBuff = (u8 *)kmalloc(sizeof(stCAM_CAL_INFO_STRUCT),GFP_KERNEL);
if(NULL == pBuff)
{
CAM_CALDB("[CAM_CAL] ioctl allocate mem failed\n");
return -ENOMEM;
}
if(_IOC_WRITE & _IOC_DIR(a_u4Command))
{
if(copy_from_user((u8 *) pBuff , (u8 *) a_u4Param, sizeof(stCAM_CAL_INFO_STRUCT)))
{ //get input structure address
kfree(pBuff);
CAM_CALDB("[CAM_CAL] ioctl copy from user failed\n");
return -EFAULT;
}
}
}
ptempbuf = (stCAM_CAL_INFO_STRUCT *)pBuff;
pWorkingBuff = (u8*)kmalloc(ptempbuf->u4Length,GFP_KERNEL);
if(NULL == pWorkingBuff)
{
kfree(pBuff);
CAM_CALDB("[CAM_CAL] ioctl allocate mem failed\n");
return -ENOMEM;
}
//fix warning MSG CAM_CALDB("[CAM_CAL] init Working buffer address 0x%x command is 0x%08x\n", pWorkingBuff, a_u4Command);
if(copy_from_user((u8*)pWorkingBuff , (u8*)ptempbuf->pu1Params, ptempbuf->u4Length))
{
kfree(pBuff);
kfree(pWorkingBuff);
CAM_CALDB("[CAM_CAL] ioctl copy from user failed\n");
return -EFAULT;
}
switch(a_u4Command)
{
case CAM_CALIOC_S_WRITE:
CAM_CALDB("[CAM_CAL] Write CMD \n");
#ifdef CAM_CALGETDLT_DEBUG
do_gettimeofday(&ktv1);
#endif
i4RetValue = iWriteData((u16)ptempbuf->u4Offset, ptempbuf->u4Length, pWorkingBuff);
#ifdef CAM_CALGETDLT_DEBUG
do_gettimeofday(&ktv2);
if(ktv2.tv_sec > ktv1.tv_sec)
{
TimeIntervalUS = ktv1.tv_usec + 1000000 - ktv2.tv_usec;
}
else
{
TimeIntervalUS = ktv2.tv_usec - ktv1.tv_usec;
}
printk("Write data %d bytes take %lu us\n",ptempbuf->u4Length, TimeIntervalUS);
#endif
break;
case CAM_CALIOC_G_READ:
CAM_CALDB("[CAM_CAL] Read CMD \n");
#ifdef CAM_CALGETDLT_DEBUG
do_gettimeofday(&ktv1);
#endif
CAM_CALDB("[CAM_CAL] offset %d \n", ptempbuf->u4Offset);
CAM_CALDB("[CAM_CAL] length %d \n", ptempbuf->u4Length);
//fix warning MSG CAM_CALDB("[CAM_CAL] Before read Working buffer address 0x%x \n", pWorkingBuff);
i4RetValue = iReadData((u16)ptempbuf->u4Offset, ptempbuf->u4Length, pWorkingBuff);
//fix warning MSG CAM_CALDB("[CAM_CAL] After read Working buffer address 0x%x \n", pWorkingBuff);
#ifdef CAM_CALGETDLT_DEBUG
do_gettimeofday(&ktv2);
if(ktv2.tv_sec > ktv1.tv_sec)
{
TimeIntervalUS = ktv1.tv_usec + 1000000 - ktv2.tv_usec;
}
else
{
TimeIntervalUS = ktv2.tv_usec - ktv1.tv_usec;
}
printk("Read data %d bytes take %lu us\n",ptempbuf->u4Length, TimeIntervalUS);
#endif
break;
default :
CAM_CALDB("[CAM_CAL] No CMD \n");
i4RetValue = -EPERM;
break;
}
if(_IOC_READ & _IOC_DIR(a_u4Command))
{
//copy data to user space buffer, keep other input paremeter unchange.
CAM_CALDB("[CAM_CAL] to user length %d \n", ptempbuf->u4Length);
//fix warning MSG CAM_CALDB("[CAM_CAL] to user Working buffer address 0x%x \n", pWorkingBuff);
if(copy_to_user((u8 __user *) ptempbuf->pu1Params , (u8 *)pWorkingBuff , ptempbuf->u4Length))
{
kfree(pBuff);
kfree(pWorkingBuff);
CAM_CALDB("[CAM_CAL] ioctl copy to user failed\n");
return -EFAULT;
}
}
kfree(pBuff);
kfree(pWorkingBuff);
return i4RetValue;
}
static u32 g_u4Opened = 0;
//#define
//Main jobs:
// 1.check for device-specified errors, device not ready.
// 2.Initialize the device if it is opened for the first time.
static int CAM_CAL_Open(struct inode * a_pstInode, struct file * a_pstFile)
{
CAM_CALDB("[S24CAM_CAL] CAM_CAL_Open\n");
spin_lock(&g_CAM_CALLock);
if(g_u4Opened)
{
spin_unlock(&g_CAM_CALLock);
return -EBUSY;
}
else
{
g_u4Opened = 1;
atomic_set(&g_CAM_CALatomic,0);
}
spin_unlock(&g_CAM_CALLock);
//#if defined(MT6572)
// do nothing
//#else
//if(TRUE != hwPowerOn(MT65XX_POWER_LDO_VCAMA, VOL_2800, "S24CS64A"))
//{
// CAM_CALDB("[CAM_CAL] Fail to enable analog gain\n");
// return -EIO;
//}
//#endif
return 0;
}
//Main jobs:
// 1.Deallocate anything that "open" allocated in private_data.
// 2.Shut down the device on last close.
// 3.Only called once on last time.
// Q1 : Try release multiple times.
static int CAM_CAL_Release(struct inode * a_pstInode, struct file * a_pstFile)
{
spin_lock(&g_CAM_CALLock);
g_u4Opened = 0;
atomic_set(&g_CAM_CALatomic,0);
spin_unlock(&g_CAM_CALLock);
return 0;
}
static const struct file_operations g_stCAM_CAL_fops =
{
.owner = THIS_MODULE,
.open = CAM_CAL_Open,
.release = CAM_CAL_Release,
//.ioctl = CAM_CAL_Ioctl
.unlocked_ioctl = CAM_CAL_Ioctl
};
#define CAM_CAL_DYNAMIC_ALLOCATE_DEVNO 1
inline static int RegisterCAM_CALCharDrv(void)
{
struct device* CAM_CAL_device = NULL;
#if CAM_CAL_DYNAMIC_ALLOCATE_DEVNO
if( alloc_chrdev_region(&g_CAM_CALdevno, 0, 1,CAM_CAL_DRVNAME) )
{
CAM_CALDB("[CAM_CAL] Allocate device no failed\n");
return -EAGAIN;
}
#else
if( register_chrdev_region( g_CAM_CALdevno , 1 , CAM_CAL_DRVNAME) )
{
CAM_CALDB("[CAM_CAL] Register device no failed\n");
return -EAGAIN;
}
#endif
//Allocate driver
g_pCAM_CAL_CharDrv = cdev_alloc();
if(NULL == g_pCAM_CAL_CharDrv)
{
unregister_chrdev_region(g_CAM_CALdevno, 1);
CAM_CALDB("[CAM_CAL] Allocate mem for kobject failed\n");
return -ENOMEM;
}
//Attatch file operation.
cdev_init(g_pCAM_CAL_CharDrv, &g_stCAM_CAL_fops);
g_pCAM_CAL_CharDrv->owner = THIS_MODULE;
//Add to system
if(cdev_add(g_pCAM_CAL_CharDrv, g_CAM_CALdevno, 1))
{
CAM_CALDB("[CAM_CAL] Attatch file operation failed\n");
unregister_chrdev_region(g_CAM_CALdevno, 1);
return -EAGAIN;
}
CAM_CAL_class = class_create(THIS_MODULE, "CAM_CALdrv");
if (IS_ERR(CAM_CAL_class)) {
int ret = PTR_ERR(CAM_CAL_class);
CAM_CALDB("Unable to create class, err = %d\n", ret);
return ret;
}
CAM_CAL_device = device_create(CAM_CAL_class, NULL, g_CAM_CALdevno, NULL, CAM_CAL_DRVNAME);
return 0;
}
inline static void UnregisterCAM_CALCharDrv(void)
{
//Release char driver
cdev_del(g_pCAM_CAL_CharDrv);
unregister_chrdev_region(g_CAM_CALdevno, 1);
device_destroy(CAM_CAL_class, g_CAM_CALdevno);
class_destroy(CAM_CAL_class);
}
//////////////////////////////////////////////////////////////////////
#ifndef CAM_CAL_ICS_REVISION
static int CAM_CAL_i2c_detect(struct i2c_client *client, int kind, struct i2c_board_info *info);
#elif 0
static int CAM_CAL_i2c_detect(struct i2c_client *client, struct i2c_board_info *info);
#else
#endif
static int CAM_CAL_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id);
static int CAM_CAL_i2c_remove(struct i2c_client *);
static const struct i2c_device_id CAM_CAL_i2c_id[] = {{CAM_CAL_DRVNAME,0},{}};
#if 0 //test110314 Please use the same I2C Group ID as Sensor
static unsigned short force[] = {CAM_CAL_I2C_GROUP_ID, S24CS64A_DEVICE_ID, I2C_CLIENT_END, I2C_CLIENT_END};
#else
//static unsigned short force[] = {CAM_CAL_I2C_GROUP_ID, S24CS64A_DEVICE_ID, I2C_CLIENT_END, I2C_CLIENT_END};
#endif
//static const unsigned short * const forces[] = { force, NULL };
//static struct i2c_client_address_data addr_data = { .forces = forces,};
static struct i2c_driver CAM_CAL_i2c_driver = {
.probe = CAM_CAL_i2c_probe,
.remove = CAM_CAL_i2c_remove,
// .detect = CAM_CAL_i2c_detect,
.driver.name = CAM_CAL_DRVNAME,
.id_table = CAM_CAL_i2c_id,
};
#ifndef CAM_CAL_ICS_REVISION
static int CAM_CAL_i2c_detect(struct i2c_client *client, int kind, struct i2c_board_info *info) {
strcpy(info->type, CAM_CAL_DRVNAME);
return 0;
}
#endif
static int CAM_CAL_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id) {
int i4RetValue = 0;
CAM_CALDB("[CAM_CAL] Attach I2C \n");
// spin_lock_init(&g_CAM_CALLock);
//get sensor i2c client
spin_lock(&g_CAM_CALLock); //for SMP
g_pstI2Cclient = client;
g_pstI2Cclient->addr = S24CS64A_DEVICE_ID>>1;
spin_unlock(&g_CAM_CALLock); // for SMP
CAM_CALDB("[CAM_CAL] g_pstI2Cclient->addr = 0x%8x \n",g_pstI2Cclient->addr);
//Register char driver
i4RetValue = RegisterCAM_CALCharDrv();
if(i4RetValue){
CAM_CALDB("[CAM_CAL] register char device failed!\n");
return i4RetValue;
}
CAM_CALDB("[CAM_CAL] Attached!! \n");
return 0;
}
static int CAM_CAL_i2c_remove(struct i2c_client *client)
{
return 0;
}
static int CAM_CAL_probe(struct platform_device *pdev)
{
return i2c_add_driver(&CAM_CAL_i2c_driver);
}
static int CAM_CAL_remove(struct platform_device *pdev)
{
i2c_del_driver(&CAM_CAL_i2c_driver);
return 0;
}
// platform structure
static struct platform_driver g_stCAM_CAL_Driver = {
.probe = CAM_CAL_probe,
.remove = CAM_CAL_remove,
.driver = {
.name = CAM_CAL_DRVNAME,
.owner = THIS_MODULE,
}
};
static struct platform_device g_stCAM_CAL_Device = {
.name = CAM_CAL_DRVNAME,
.id = 0,
.dev = {
}
};
static int __init CAM_CAL_i2C_init(void)
{
i2c_register_board_info(CAM_CAL_I2C_BUSNUM, &kd_cam_cal_dev, 1);
if(platform_driver_register(&g_stCAM_CAL_Driver)){
CAM_CALDB("failed to register CAM_CAL driver\n");
return -ENODEV;
}
if (platform_device_register(&g_stCAM_CAL_Device))
{
CAM_CALDB("failed to register CAM_CAL driver\n");
return -ENODEV;
}
return 0;
}
static void __exit CAM_CAL_i2C_exit(void)
{
platform_driver_unregister(&g_stCAM_CAL_Driver);
}
module_init(CAM_CAL_i2C_init);
module_exit(CAM_CAL_i2C_exit);
MODULE_DESCRIPTION("CAM_CAL driver");
MODULE_AUTHOR("Sean Lin <Sean.Lin@Mediatek.com>");
MODULE_LICENSE("GPL");
arch/arm/mach-mt8127/ford/cam_cal/dummy_cam_cal.h
+30
View File
@@ -0,0 +1,30 @@
/*****************************************************************************
*
* Filename:
* ---------
* S-24CS64A.h
*
* Project:
* --------
* ALPS
*
* Description:
* ------------
* Header file of CAM_CAL driver
*
*
* Author:
* -------
* Ronnie Lai (MTK01420)
*
*============================================================================*/
#ifndef __CAM_CAL_H
#define __CAM_CAL_H
#define CAM_CAL_DEV_MAJOR_NUMBER 226
/* CAM_CAL READ/WRITE ID */
#define S24CS64A_DEVICE_ID 0xAB //0xFE //
#endif /* __CAM_CAL_H */
arch/arm/mach-mt8127/ford/cam_cal/inc/cam_cal.h
+27
View File
@@ -0,0 +1,27 @@
#ifndef _CAM_CAL_H
#define _CAM_CAL_H
#include <linux/ioctl.h>
#define CAM_CALAGIC 'i'
//IOCTRL(inode * ,file * ,cmd ,arg )
//S means "set through a ptr"
//T means "tell by a arg value"
//G means "get by a ptr"
//Q means "get by return a value"
//X means "switch G and S atomically"
//H means "switch T and Q atomically"
/*******************************************************************************
*
********************************************************************************/
//CAM_CAL write
#define CAM_CALIOC_S_WRITE _IOW(CAM_CALAGIC,0,stCAM_CAL_INFO_STRUCT)
//CAM_CAL read
#define CAM_CALIOC_G_READ _IOWR(CAM_CALAGIC,5,stPCAM_CAL_INFO_STRUCT)
#endif //_CAM_CAL_H
arch/arm/mach-mt8127/ford/cam_cal/inc/cam_cal_define.h
+10
View File
@@ -0,0 +1,10 @@
#ifndef _CAM_CAL_DATA_H
#define _CAM_CAL_DATA_H
typedef struct{
u32 u4Offset;
u32 u4Length;
u8 * pu1Params;
}stCAM_CAL_INFO_STRUCT, *stPCAM_CAL_INFO_STRUCT;
#endif //_CAM_CAL_DATA_H
arch/arm/mach-mt8127/ford/camera/camera/Makefile
Executable
+4
View File
@@ -0,0 +1,4 @@
include $(srctree)/drivers/misc/mediatek/Makefile.custom
obj-y += dummyds.o
obj-y += kd_camera_hw.o
drivers/misc/mediatek/hdmi/nxp_tda19989/dummy.c → arch/arm/mach-mt8127/ford/camera/camera/dummyds.c
View File
arch/arm/mach-mt8127/ford/camera/camera/kd_camera_hw.c
+1967
View File
File diff suppressed because it is too large Load Diff
arch/arm/mach-mt8127/ford/camera/camera/kd_camera_hw.h
+78
View File
@@ -0,0 +1,78 @@
#ifndef _KD_CAMERA_HW_H_
#define _KD_CAMERA_HW_H_
#include <mach/mt_gpio.h>
#include <mach/mt_pm_ldo.h>
//
//Power
#ifdef CONFIG_MTK_PMIC_MT6397
#define CAMERA_POWER_VCAM_A MT65XX_POWER_LDO_VCAMA
#define CAMERA_POWER_VCAM_D MT65XX_POWER_LDO_VCAMD
#define CAMERA_POWER_VCAM_A2 MT65XX_POWER_LDO_VCAMAF
#define CAMERA_POWER_VCAM_D2 MT65XX_POWER_LDO_VCAMIO
#else
#define CAMERA_POWER_VCAM_A MT6323_POWER_LDO_VCAMA
#define CAMERA_POWER_VCAM_D MT6323_POWER_LDO_VCAMD
#define CAMERA_POWER_VCAM_A2 MT6323_POWER_LDO_VCAM_AF
#define CAMERA_POWER_VCAM_D2 MT6323_POWER_LDO_VCAM_IO
#endif
//FIXME, should defined in DCT tool
//
/*
#ifndef GPIO_CAMERA_LDO_EN_PIN
#define GPIO_CAMERA_LDO_EN_PIN GPIO94
#endif
//
#ifndef GPIO_CAMERA_CMRST_PIN
#define GPIO_CAMERA_CMRST_PIN GPIO9
#endif
//
#ifndef GPIO_CAMERA_CMRST_PIN_M_GPIO
#define GPIO_CAMERA_CMRST_PIN_M_GPIO GPIO_MODE_00
#endif
//
#ifndef GPIO_CAMERA_CMPDN_PIN
#define GPIO_CAMERA_CMPDN_PIN GPIO10
#endif
//
#ifndef GPIO_CAMERA_LDO_EN_PIN_M_GPIO
#define GPIO_CAMERA_LDO_EN_PIN_M_GPIO GPIO_MODE_00
#endif
//
#ifndef GPIO_CAMERA_CMPDN_PIN_M_GPIO
#define GPIO_CAMERA_CMPDN_PIN_M_GPIO GPIO_MODE_00
#endif
//
#ifndef GPIO_CAMERA_CMRST1_PIN
#define GPIO_CAMERA_CMRST1_PIN GPIO3
#endif
//
#ifndef GPIO_CAMERA_CMRST1_PIN_M_GPIO
#define GPIO_CAMERA_CMRST1_PIN_M_GPIO GPIO_MODE_00
#endif
//
#ifndef GPIO_CAMERA_CMPDN1_PIN
#define GPIO_CAMERA_CMPDN1_PIN GPIO4
#endif
//
#ifndef GPIO_CAMERA_CMPDN1_PIN_M_GPIO
#define GPIO_CAMERA_CMPDN1_PIN_M_GPIO GPIO_MODE_00
#endif
//i2c id for sensor device, MT8320_fpga, the I2C is attached on 1
#define IMG_SENSOR_I2C_GROUP_ID 0
#define A60373_WRITE_ID (0xC0)
#define A60373_READ_ID (0xC1)
*/
#endif
arch/arm/mach-mt8127/ford/core/Makefile
Executable
+4
View File
@@ -0,0 +1,4 @@
include $(srctree)/drivers/misc/mediatek/Makefile.custom
obj-y := board.o
arch/arm/mach-mt8127/ford/core/board-custom.h
+119
View File
@@ -0,0 +1,119 @@
#ifndef __ARCH_ARM_MACH_MT6575_CUSTOM_BOARD_H
#define __ARCH_ARM_MACH_MT6575_CUSTOM_BOARD_H
#include <generated/autoconf.h>
/*=======================================================================*/
/* MT6575 SD */
/*=======================================================================*/
#define CFG_DEV_MSDC0
#define CFG_DEV_MSDC1
//#define CFG_DEV_MSDC2
//#define CFG_DEV_MSDC3
//#define CFG_DEV_MSDC4
#if defined(CONFIG_MTK_COMBO) || defined(CONFIG_MTK_COMBO_MODULE)
/*
SDIO slot index number used by connectivity combo chip:
0: invalid (used by memory card)
1: MSDC1
2: MSDC2
*/
#define CONFIG_MTK_WCN_CMB_SDIO_SLOT (3) /* MSDC3 */
#else
#undef CONFIG_MTK_WCN_CMB_SDIO_SLOT
#endif
/*For MT6582 platform we disable COMBO SDIO SLOT defination*/
#undef CONFIG_MTK_WCN_CMB_SDIO_SLOT
#if 0 /* FIXME. */
/*=======================================================================*/
/* MT6575 UART */
/*=======================================================================*/
#define CFG_DEV_UART1
#define CFG_DEV_UART2
#define CFG_DEV_UART3
#define CFG_DEV_UART4
#define CFG_UART_PORTS (4)
/*=======================================================================*/
/* MT6575 I2C */
/*=======================================================================*/
#define CFG_DEV_I2C
//#define CFG_I2C_HIGH_SPEED_MODE
//#define CFG_I2C_DMA_MODE
/*=======================================================================*/
/* MT6575 ADB */
/*=======================================================================*/
#define ADB_SERIAL "E1K"
#endif
/*=======================================================================*/
/* MT6575 NAND FLASH */
/*=======================================================================*/
#if 0
#define RAMDOM_READ 1<<0
#define CACHE_READ 1<<1
/*******************************************************************************
* NFI & ECC Configuration
*******************************************************************************/
typedef struct
{
u16 id; //deviceid+menuid
u8 addr_cycle;
u8 iowidth;
u16 totalsize;
u16 blocksize;
u16 pagesize;
u32 timmingsetting;
char devciename[14];
u32 advancedmode; //
}flashdev_info,*pflashdev_info;
static const flashdev_info g_FlashTable[]={
//micro
{0xAA2C, 5, 8, 256, 128, 2048, 0x01113, "MT29F2G08ABD", 0},
{0xB12C, 4, 16, 128, 128, 2048, 0x01113, "MT29F1G16ABC", 0},
{0xBA2C, 5, 16, 256, 128, 2048, 0x01113, "MT29F2G16ABD", 0},
{0xAC2C, 5, 8, 512, 128, 2048, 0x01113, "MT29F4G08ABC", 0},
{0xBC2C, 5, 16, 512, 128, 2048, 0x44333, "MT29F4G16ABD", 0},
//samsung
{0xBAEC, 5, 16, 256, 128, 2048, 0x01123, "K522H1GACE", 0},
{0xBCEC, 5, 16, 512, 128, 2048, 0x01123, "K524G2GACB", 0},
{0xDAEC, 5, 8, 256, 128, 2048, 0x33222, "K9F2G08U0A", RAMDOM_READ},
{0xF1EC, 4, 8, 128, 128, 2048, 0x01123, "K9F1G08U0A", RAMDOM_READ},
{0xAAEC, 5, 8, 256, 128, 2048, 0x01123, "K9F2G08R0A", 0},
//hynix
{0xD3AD, 5, 8, 1024, 256, 2048, 0x44333, "HY27UT088G2A", 0},
{0xA1AD, 4, 8, 128, 128, 2048, 0x01123, "H8BCSOPJOMCP", 0},
{0xBCAD, 5, 16, 512, 128, 2048, 0x01123, "H8BCSOUNOMCR", 0},
{0xBAAD, 5, 16, 256, 128, 2048, 0x01123, "H8BCSOSNOMCR", 0},
//toshiba
{0x9598, 5, 16, 816, 128, 2048, 0x00113, "TY9C000000CMG", 0},
{0x9498, 5, 16, 375, 128, 2048, 0x00113, "TY9C000000CMG", 0},
{0xC198, 4, 16, 128, 128, 2048, 0x44333, "TC58NWGOS8C", 0},
{0xBA98, 5, 16, 256, 128, 2048, 0x02113, "TC58NYG1S8C", 0},
//st-micro
{0xBA20, 5, 16, 256, 128, 2048, 0x01123, "ND02CGR4B2DI6", 0},
// elpida
{0xBC20, 5, 16, 512, 128, 2048, 0x01123, "04GR4B2DDI6", 0},
{0x0000, 0, 0, 0, 0, 0, 0, "xxxxxxxxxxxxx", 0}
};
#endif
#define NFI_DEFAULT_ACCESS_TIMING (0x44333)
//uboot only support 1 cs
#define NFI_CS_NUM (2)
#define NFI_DEFAULT_CS (0)
#define USE_AHB_MODE (1)
#define PLATFORM_EVB (1)
#endif /* __ARCH_ARM_MACH_MT6575_CUSTOM_BOARD_H */
arch/arm/mach-mt8127/ford/core/board.c
+863
View File
@@ -0,0 +1,863 @@
/* system header files */
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/mutex.h>
#include <linux/uaccess.h>
#include <linux/syscalls.h>
#include <linux/mtd/nand.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/setup.h>
#include <mach/system.h>
#include <mach/board.h>
#include <mach/hardware.h>
#include <mach/mt_gpio.h>
#include <mach/mt_bt.h>
#include <mach/eint.h>
#include <mach/mtk_rtc.h>
#include <mach/mt_typedefs.h>
// Fix-me: marked for early porting
#include <cust_gpio_usage.h>
#include <cust_eint.h>
#include <mach/upmu_hw.h>
#include "board-custom.h"
#if defined(CONFIG_MTK_COMBO) || defined(CONFIG_MTK_COMBO_MODULE)
#include <mach/mtk_wcn_cmb_stub.h>
#endif
#if defined(CONFIG_MTK_WCN_CMB_SDIO_SLOT)
static sdio_irq_handler_t mtk_wcn_cmb_sdio_eirq_handler = NULL;
int mtk_wcn_sdio_irq_flag_set (int falg);
static atomic_t sdio_irq_enable_flag;
static pm_callback_t mtk_wcn_cmb_sdio_pm_cb = NULL;
static void *mtk_wcn_cmb_sdio_pm_data = NULL;
static void *mtk_wcn_cmb_sdio_eirq_data = NULL;
//static pm_message_t mt_wifi_pm_state = { .event = PM_EVENT_HIBERNATE };
//static int mt_wifi_pm_late_cb = 0;
const static u32 mtk_wcn_cmb_sdio_eint_pin = GPIO_WIFI_EINT_PIN;
const static u32 mtk_wcn_cmb_sdio_eint_num = CUST_EINT_WIFI_NUM;
const static u32 mtk_wcn_cmb_sdio_eint_m_eint = GPIO_WIFI_EINT_PIN_M_EINT;
const static u32 mtk_wcn_cmb_sdio_eint_m_gpio = GPIO_WIFI_EINT_PIN_M_GPIO;
#if (CONFIG_MTK_WCN_CMB_SDIO_SLOT == 0)
static unsigned char combo_port_pwr_map[4] = {0x0, 0xFF, 0xFF, 0xFF};
/*
index: port number of combo chip (1:SDIO1, 2:SDIO2, no SDIO0)
value: slot power status of (0:off, 1:on, 0xFF:invalid)
*/
#elif (CONFIG_MTK_WCN_CMB_SDIO_SLOT == 1)
static unsigned char combo_port_pwr_map[4] = {0xFF, 0x0, 0xFF, 0xFF};
/*
index: port number of combo chip (1:SDIO1, 2:SDIO2, no SDIO0)
value: slot power status of (0:off, 1:on, 0xFF:invalid)
*/
#elif (CONFIG_MTK_WCN_CMB_SDIO_SLOT == 2)
static unsigned char combo_port_pwr_map[4] = {0xFF, 0xFF, 0x0, 0xFF};
/*
index: port number of combo chip (1:SDIO1, 2:SDIO2, no SDIO0)
value: slot power status of (0:off, 1:on, 0xFF:invalid)
*/
#elif (CONFIG_MTK_WCN_CMB_SDIO_SLOT == 3)
static unsigned char combo_port_pwr_map[4] = {0xFF, 0xFF, 0xFF, 0x0};
/*
index: port number of combo chip (1:SDIO1, 2:SDIO2, no SDIO0)
value: slot power status of (0:off, 1:on, 0xFF:invalid)
*/
#else
#error "unsupported CONFIG_MTK_WCN_CMB_SDIO_SLOT" CONFIG_MTK_WCN_CMB_SDIO_SLOT
#endif
#else
#if 0
static sdio_irq_handler_t mt_wifi_irq_handler = NULL;
static pm_message_t mt_wifi_pm_state = { .event = PM_EVENT_HIBERNATE };
static pm_callback_t mt_wifi_pm_cb = NULL;
static void *mt_wifi_pm_data = NULL;
static void *mt_wifi_irq_data = NULL;
static int mt_wifi_pm_late_cb = 0;
#endif
/* temp solution to avoid compile error */
#ifndef CUST_EINT_WIFI_NUM
#define CUST_EINT_WIFI_NUM 0
#endif
#ifndef CUST_EINT_WIFI_TYPE
#define CUST_EINT_WIFI_TYPE 0
#endif
#endif
/*=======================================================================*/
/* Board Specific Devices Power Management */
/*=======================================================================*/
extern kal_bool pmic_chrdet_status(void);
extern U32 pmic_config_interface (U32 RegNum, U32 val, U32 MASK, U32 SHIFT);
extern U32 pmic_read_interface (U32 RegNum, U32 *val, U32 MASK, U32 SHIFT);
extern int accdet_cable_type_state(void);
void mt_power_off(void)
{
#ifdef CONFIG_MTK_PMIC_MT6397
int ret_val=0;
int reg_val=0;
#endif
int bbpu_down = 0;
printk("mt_power_off\n");
#ifdef CONFIG_MTK_PMIC_MT6397
//Enable CA15 by default for different PMIC behavior
pmic_config_interface(VCA15_CON7, 0x1, PMIC_VCA15_EN_MASK, PMIC_VCA15_EN_SHIFT);
pmic_config_interface(VSRMCA15_CON7, 0x1, PMIC_VSRMCA15_EN_MASK, PMIC_VSRMCA15_EN_SHIFT);
udelay(200);
ret_val=pmic_read_interface(VCA15_CON7, &reg_val, 0xFFFF, 0);
printk("Reg[0x%x]=0x%x\n", VCA15_CON7, reg_val);
ret_val=pmic_read_interface(VSRMCA15_CON7, &reg_val, 0xFFFF, 0);
printk("Reg[0x%x]=0x%x\n", VSRMCA15_CON7, reg_val);
#endif
#ifdef CONFIG_MTK_AUTO_POWER_ON_WITH_CHARGER
if (pmic_chrdet_status() == KAL_TRUE)
rtc_mark_enter_kpoc();
#endif
// Set the right PMIC Audio Power off Sequence
if (accdet_cable_type_state())
{
pmic_config_interface(AUDTOP_CON6, 0x17E2, 0xFFFF, 0);
mdelay(3000);
pmic_config_interface(AUDTOP_CON6, 0x15E2, 0xFFFF, 0);
}
/* pull PWRBB low */
if (pmic_chrdet_status() == KAL_FALSE) {
bbpu_down = 1;
rtc_bbpu_power_down();
}
while (1) {
pr_info("check charger\n");
if (pmic_chrdet_status() == KAL_TRUE) {
#ifdef CONFIG_MTK_AUTO_POWER_ON_WITH_CHARGER
arch_reset(0, "enter_kpoc");
#else
arch_reset(0, "charger");
#endif
} else if (bbpu_down == 0) {
bbpu_down = 1;
rtc_bbpu_power_down();
}
}
}
/*=======================================================================*/
/* Board Specific Devices */
/*=======================================================================*/
/*GPS driver*/
/*FIXME: remove mt3326 notation */
struct mt3326_gps_hardware mt3326_gps_hw = {
.ext_power_on = NULL,
.ext_power_off = NULL,
};
/*=======================================================================*/
/* Board Specific Devices Init */
/*=======================================================================*/
#ifdef MTK_BT_SUPPORT
void mt_bt_power_on(void)
{
printk(KERN_INFO "+mt_bt_power_on\n");
#if defined(CONFIG_MTK_COMBO) || defined(CONFIG_MTK_COMBO_MODULE)
/* combo chip product */
/*
* Ignore rfkill0/state call. Controll BT power on/off through device /dev/stpbt.
*/
#else
/* standalone product */
#endif
printk(KERN_INFO "-mt_bt_power_on\n");
}
EXPORT_SYMBOL(mt_bt_power_on);
void mt_bt_power_off(void)
{
printk(KERN_INFO "+mt_bt_power_off\n");
#if defined(CONFIG_MTK_COMBO) || defined(CONFIG_MTK_COMBO_MODULE)
/* combo chip product */
/*
* Ignore rfkill0/state call. Controll BT power on/off through device /dev/stpbt.
*/
#else
/* standalone product */
#endif
printk(KERN_INFO "-mt_bt_power_off\n");
}
EXPORT_SYMBOL(mt_bt_power_off);
int mt_bt_suspend(pm_message_t state)
{
printk(KERN_INFO "+mt_bt_suspend\n");
printk(KERN_INFO "-mt_bt_suspend\n");
return MT_BT_OK;
}
int mt_bt_resume(pm_message_t state)
{
printk(KERN_INFO "+mt_bt_resume\n");
printk(KERN_INFO "-mt_bt_resume\n");
return MT_BT_OK;
}
#endif
#if defined(CONFIG_MTK_WCN_CMB_SDIO_SLOT)
static void mtk_wcn_cmb_sdio_enable_eirq(void)
{
mt_eint_unmask(mtk_wcn_cmb_sdio_eint_num);/* CUST_EINT_WIFI_NUM */
}
static void mtk_wcn_cmb_sdio_disable_eirq(void)
{
mt_eint_mask(mtk_wcn_cmb_sdio_eint_num); /* CUST_EINT_WIFI_NUM */
}
static void mtk_wcn_cmb_sdio_eirq_handler_stub(void)
{
if ((NULL != mtk_wcn_cmb_sdio_eirq_handler) && (0 != atomic_read(&sdio_irq_enable_flag))) {
mtk_wcn_cmb_sdio_eirq_handler(mtk_wcn_cmb_sdio_eirq_data);
}
}
static void mtk_wcn_cmb_sdio_request_eirq(sdio_irq_handler_t irq_handler, void *data)
{
mtk_wcn_sdio_irq_flag_set (0);
mtk_wcn_cmb_sdio_eirq_data = data;
mtk_wcn_cmb_sdio_eirq_handler = irq_handler;
#if CUST_EINT_WIFI_DEBOUNCE_EN
mt_eint_set_hw_debounce(mtk_wcn_cmb_sdio_eint_num, CUST_EINT_WIFI_DEBOUNCE_CN); /*CUST_EINT_WIFI_NUM */
#endif
mt_set_gpio_pull_enable(mtk_wcn_cmb_sdio_eint_pin, GPIO_PULL_ENABLE);
mt_set_gpio_pull_select(mtk_wcn_cmb_sdio_eint_pin, GPIO_PULL_UP);
mt_eint_registration(mtk_wcn_cmb_sdio_eint_num/*CUST_EINT_WIFI_NUM */,
CUST_EINT_WIFI_TYPE,
mtk_wcn_cmb_sdio_eirq_handler_stub,
0);
mt_eint_mask(mtk_wcn_cmb_sdio_eint_num);/*CUST_EINT_WIFI_NUM */
}
static void mtk_wcn_cmb_sdio_register_pm(pm_callback_t pm_cb, void *data)
{
printk( KERN_INFO "mtk_wcn_cmb_sdio_register_pm (0x%p, 0x%p)\n", pm_cb, data);
/* register pm change callback */
mtk_wcn_cmb_sdio_pm_cb = pm_cb;
mtk_wcn_cmb_sdio_pm_data = data;
}
static void mtk_wcn_cmb_sdio_on (int sdio_port_num) {
pm_message_t state = { .event = PM_EVENT_USER_RESUME };
printk(KERN_INFO "mtk_wcn_cmb_sdio_on (%d) \n", sdio_port_num);
/* 1. disable sdio eirq */
mtk_wcn_cmb_sdio_disable_eirq();
mt_set_gpio_pull_enable(mtk_wcn_cmb_sdio_eint_pin, GPIO_PULL_DISABLE); /* GPIO_WIFI_EINT_PIN */
mt_set_gpio_mode(mtk_wcn_cmb_sdio_eint_pin, mtk_wcn_cmb_sdio_eint_m_eint); /* EINT mode */
/* 2. call sd callback */
if (mtk_wcn_cmb_sdio_pm_cb) {
//printk(KERN_INFO "mtk_wcn_cmb_sdio_pm_cb(PM_EVENT_USER_RESUME, 0x%p, 0x%p) \n", mtk_wcn_cmb_sdio_pm_cb, mtk_wcn_cmb_sdio_pm_data);
mtk_wcn_cmb_sdio_pm_cb(state, mtk_wcn_cmb_sdio_pm_data);
}
else {
printk(KERN_WARNING "mtk_wcn_cmb_sdio_on no sd callback!!\n");
}
}
static void mtk_wcn_cmb_sdio_off (int sdio_port_num) {
pm_message_t state = { .event = PM_EVENT_USER_SUSPEND };
printk(KERN_INFO "mtk_wcn_cmb_sdio_off (%d) \n", sdio_port_num);
/* 1. call sd callback */
if (mtk_wcn_cmb_sdio_pm_cb) {
//printk(KERN_INFO "mtk_wcn_cmb_sdio_off(PM_EVENT_USER_SUSPEND, 0x%p, 0x%p) \n", mtk_wcn_cmb_sdio_pm_cb, mtk_wcn_cmb_sdio_pm_data);
mtk_wcn_cmb_sdio_pm_cb(state, mtk_wcn_cmb_sdio_pm_data);
}
else {
printk(KERN_WARNING "mtk_wcn_cmb_sdio_off no sd callback!!\n");
}
/* 2. disable sdio eirq */
mtk_wcn_cmb_sdio_disable_eirq();
/*printk(KERN_INFO "[mt6620] set WIFI_EINT input pull down\n");*/
mt_set_gpio_mode(mtk_wcn_cmb_sdio_eint_pin, mtk_wcn_cmb_sdio_eint_m_gpio); /* GPIO mode */
mt_set_gpio_dir(mtk_wcn_cmb_sdio_eint_pin, GPIO_DIR_IN);
mt_set_gpio_pull_select(mtk_wcn_cmb_sdio_eint_pin, GPIO_PULL_UP);
mt_set_gpio_pull_enable(mtk_wcn_cmb_sdio_eint_pin, GPIO_PULL_ENABLE);
}
int board_sdio_ctrl (unsigned int sdio_port_num, unsigned int on) {
#if defined(CONFIG_MTK_WCN_CMB_SDIO_SLOT)
sdio_port_num = CONFIG_MTK_WCN_CMB_SDIO_SLOT;
printk(KERN_WARNING "mt_combo_sdio_ctrl: force set sdio port to (%d)\n", sdio_port_num);
#endif
if ((sdio_port_num >= 4) || (combo_port_pwr_map[sdio_port_num] == 0xFF) ) {
/* invalid sdio port number or slot mapping */
printk(KERN_WARNING "mt_mtk_wcn_cmb_sdio_ctrl invalid port(%d, %d)\n", sdio_port_num, combo_port_pwr_map[sdio_port_num]);
return -1;
}
/*printk(KERN_INFO "mt_mtk_wcn_cmb_sdio_ctrl (%d, %d)\n", sdio_port_num, on);*/
if (!combo_port_pwr_map[sdio_port_num] && on) {
printk(KERN_INFO "board_sdio_ctrl force off before on\n");
mtk_wcn_cmb_sdio_off(sdio_port_num);
combo_port_pwr_map[sdio_port_num] = 0;
/* off -> on */
mtk_wcn_cmb_sdio_on(sdio_port_num);
combo_port_pwr_map[sdio_port_num] = 1;
}
else if (combo_port_pwr_map[sdio_port_num] && !on) {
/* on -> off */
mtk_wcn_cmb_sdio_off(sdio_port_num);
combo_port_pwr_map[sdio_port_num] = 0;
}
else {
return -2;
}
return 0;
}
EXPORT_SYMBOL(board_sdio_ctrl);
int mtk_wcn_sdio_irq_flag_set (int flag)
{
if (0 != flag)
{
atomic_set(&sdio_irq_enable_flag, 1);
}
else
{
atomic_set(&sdio_irq_enable_flag, 0);
}
printk(KERN_INFO "sdio_irq_enable_flag:%d\n", atomic_read(&sdio_irq_enable_flag));
return atomic_read(&sdio_irq_enable_flag);
}
EXPORT_SYMBOL(mtk_wcn_sdio_irq_flag_set);
#endif
#if defined(CONFIG_WLAN)
#if !defined(CONFIG_MTK_WCN_CMB_SDIO_SLOT)
#if 0
static void mt_wifi_enable_irq(void)
{
mt_eint_unmask(CUST_EINT_WIFI_NUM);
}
static void mt_wifi_disable_irq(void)
{
mt_eint_mask(CUST_EINT_WIFI_NUM);
}
static void mt_wifi_eirq_handler(void)
{
if (mt_wifi_irq_handler) {
mt_wifi_irq_handler(mt_wifi_irq_data);
}
}
static void mt_wifi_request_irq(sdio_irq_handler_t irq_handler, void *data)
{
#if CUST_EINT_WIFI_SENSITIVE
mt_eint_set_sens(CUST_EINT_WIFI_NUM, CUST_EINT_WIFI_SENSITIVE);
#endif
#if CUST_EINT_WIFI_DEBOUNCE_EN
mt_eint_set_hw_debounce(CUST_EINT_WIFI_NUM, CUST_EINT_WIFI_DEBOUNCE_CN);
#endif
mt_eint_registration(CUST_EINT_WIFI_NUM,
CUST_EINT_WIFI_TYPE,
mt_wifi_eirq_handler,
0);
mt_eint_mask(CUST_EINT_WIFI_NUM);
mt_wifi_irq_handler = irq_handler;
mt_wifi_irq_data = data;
}
static void mt_wifi_register_pm(pm_callback_t pm_cb, void *data)
{
/* register pm change callback */
mt_wifi_pm_cb = pm_cb;
mt_wifi_pm_data = data;
}
#endif
#endif /* end of !defined(CONFIG_MTK_WCN_CMB_SDIO_SLOT) */
int mt_wifi_resume(pm_message_t state)
{
int evt = state.event;
if (evt != PM_EVENT_USER_RESUME && evt != PM_EVENT_RESUME) {
return -1;
}
/*printk(KERN_INFO "[WIFI] %s Resume\n", evt == PM_EVENT_RESUME ? "PM":"USR");*/
#if defined(CONFIG_MTK_COMBO) || defined(CONFIG_MTK_COMBO_MODULE)
/* combo chip product: notify combo driver to turn on Wi-Fi */
#endif
return 0;
}
int mt_wifi_suspend(pm_message_t state)
{
int evt = state.event;
#if defined(CONFIG_MTK_WCN_CMB_SDIO_SLOT)
static int is_1st_suspend_from_boot = 1;
#endif
if (evt != PM_EVENT_USER_SUSPEND && evt != PM_EVENT_SUSPEND) {
return -1;
}
#if defined(CONFIG_MTK_COMBO) || defined(CONFIG_MTK_COMBO_MODULE)
#if defined(CONFIG_MTK_WCN_CMB_SDIO_SLOT)
/* combo chip product: notify combo driver to turn on Wi-Fi */
if (is_1st_suspend_from_boot) {
pm_message_t state = { .event = PM_EVENT_USER_SUSPEND };
if (mtk_wcn_cmb_sdio_pm_cb) {
is_1st_suspend_from_boot = 0;
/* *** IMPORTANT DEPENDENDY***
RFKILL: set wifi and bt suspend by default in probe()
MT6573-SD: sd host is added to MMC stack and suspend is ZERO by default
(which means NOT suspended).
When boot up, RFKILL will set wifi off and this function gets
called. In order to successfully resume wifi at 1st time, pm_cb here
shall be called once to let MT6573-SD do sd host suspend and remove
sd host from MMC. Then wifi can be turned on successfully.
Boot->SD host added to MMC (suspend=0)->RFKILL set wifi off
->SD host removed from MMC (suspend=1)->RFKILL set wifi on
*/
printk(KERN_INFO "1st mt_wifi_suspend (PM_EVENT_USER_SUSPEND) \n");
(*mtk_wcn_cmb_sdio_pm_cb)(state, mtk_wcn_cmb_sdio_pm_data);
}
else {
printk(KERN_WARNING "1st mt_wifi_suspend but no sd callback!!\n");
}
}
else {
/* combo chip product, notify combo driver */
}
#endif
#else
#endif
return 0;
}
void mt_wifi_power_on(void)
{
pm_message_t state = { .event = PM_EVENT_USER_RESUME };
(void)mt_wifi_resume(state);
}
EXPORT_SYMBOL(mt_wifi_power_on);
void mt_wifi_power_off(void)
{
pm_message_t state = { .event = PM_EVENT_USER_SUSPEND };
(void)mt_wifi_suspend(state);
}
EXPORT_SYMBOL(mt_wifi_power_off);
#endif /* end of defined(CONFIG_WLAN) */
/* Board Specific Devices */
/*=======================================================================*/
/*=======================================================================*/
/* Board Specific Devices Init */
/*=======================================================================*/
/*=======================================================================*/
/* Board Devices Capability */
/*=======================================================================*/
#define MSDC_SDCARD_FLAG (MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE | MSDC_HIGHSPEED)
#define MSDC_SDIO_FLAG (MSDC_EXT_SDIO_IRQ | MSDC_HIGHSPEED)
#if defined(CFG_DEV_MSDC0)
#if defined(CONFIG_MTK_WCN_CMB_SDIO_SLOT) && (CONFIG_MTK_WCN_CMB_SDIO_SLOT == 0)
struct msdc_hw msdc0_hw = {
.clk_src = MSDC_CLKSRC_200MHZ,
.cmd_edge = MSDC_SMPL_FALLING,
.rdata_edge = MSDC_SMPL_FALLING,
.wdata_edge = MSDC_SMPL_FALLING,
.clk_drv = 0,
.cmd_drv = 0,
.dat_drv = 0,
.data_pins = 4,
.data_offset = 0,
//MT6620 use External IRQ, wifi uses high speed. here wifi manage his own suspend and resume, does not support hot plug
.flags = MSDC_SDIO_FLAG,//MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE,(this flag is for SD card)
.dat0rddly = 0,
.dat1rddly = 0,
.dat2rddly = 0,
.dat3rddly = 0,
.dat4rddly = 0,
.dat5rddly = 0,
.dat6rddly = 0,
.dat7rddly = 0,
.datwrddly = 0,
.cmdrrddly = 0,
.cmdrddly = 0,
.host_function = MSDC_SDIO,
.boot = 0,
.request_sdio_eirq = mtk_wcn_cmb_sdio_request_eirq,
.enable_sdio_eirq = mtk_wcn_cmb_sdio_enable_eirq,
.disable_sdio_eirq = mtk_wcn_cmb_sdio_disable_eirq,
.register_pm = mtk_wcn_cmb_sdio_register_pm,
};
#else
struct msdc_hw msdc0_hw = {
.clk_src = MSDC_CLKSRC_200MHZ,
.cmd_edge = MSDC_SMPL_FALLING,
.rdata_edge = MSDC_SMPL_FALLING,
.wdata_edge = MSDC_SMPL_FALLING,
.clk_drv = 4,
.cmd_drv = 2,
.dat_drv = 2,
.data_pins = 8,
.data_offset = 0,
.flags = MSDC_SYS_SUSPEND | MSDC_HIGHSPEED | MSDC_UHS1 | MSDC_DDR,
.dat0rddly = 0,
.dat1rddly = 0,
.dat2rddly = 0,
.dat3rddly = 0,
.dat4rddly = 0,
.dat5rddly = 0,
.dat6rddly = 0,
.dat7rddly = 0,
.datwrddly = 0,
.cmdrrddly = 0,
.cmdrddly = 0,
.host_function = MSDC_EMMC,
.boot = MSDC_BOOT_EN,
};
#endif
#endif
#if defined(CFG_DEV_MSDC1)
#if defined(CONFIG_MTK_WCN_CMB_SDIO_SLOT) && (CONFIG_MTK_WCN_CMB_SDIO_SLOT == 1)
struct msdc_hw msdc1_hw = {
.clk_src = MSDC_CLKSRC_200MHZ,
.cmd_edge = MSDC_SMPL_FALLING,
.rdata_edge = MSDC_SMPL_FALLING,
.wdata_edge = MSDC_SMPL_FALLING,
.clk_drv = 4,
.cmd_drv = 3,
.dat_drv = 3,
.clk_drv_sd_18 = 4, /* sdr104 mode */
.cmd_drv_sd_18 = 4,
.dat_drv_sd_18 = 4,
.clk_drv_sd_18_sdr50 = 4, /* sdr50 mode */
.cmd_drv_sd_18_sdr50 = 4,
.dat_drv_sd_18_sdr50 = 4,
.clk_drv_sd_18_ddr50 = 4, /* ddr50 mode */
.cmd_drv_sd_18_ddr50 = 4,
.dat_drv_sd_18_ddr50 = 4,
.data_pins = 4,
.data_offset = 0,
.flags = MSDC_SDIO_FLAG,
.dat0rddly = 0,
.dat1rddly = 0,
.dat2rddly = 0,
.dat3rddly = 0,
.dat4rddly = 0,
.dat5rddly = 0,
.dat6rddly = 0,
.dat7rddly = 0,
.datwrddly = 0,
.cmdrrddly = 0,
.cmdrddly = 0,
.host_function = MSDC_SDIO,
.boot = 0,
.cd_level = MSDC_CD_LOW,
};
#else
struct msdc_hw msdc1_hw = {
.clk_src = MSDC_CLKSRC_200MHZ,
.cmd_edge = MSDC_SMPL_FALLING,
.rdata_edge = MSDC_SMPL_FALLING,
.wdata_edge = MSDC_SMPL_FALLING,
.clk_drv = 6,
.cmd_drv = 6,
.dat_drv = 6,
.clk_drv_sd_18 = 3, /* sdr104 mode */
.cmd_drv_sd_18 = 3,
.dat_drv_sd_18 = 2,
.clk_drv_sd_18_sdr50 = 3, /* sdr50 mode */
.cmd_drv_sd_18_sdr50 = 3,
.dat_drv_sd_18_sdr50 = 2,
.clk_drv_sd_18_ddr50 = 3, /* ddr50 mode */
.cmd_drv_sd_18_ddr50 = 3,
.dat_drv_sd_18_ddr50 = 2,
.data_pins = 4,
.data_offset = 0,
#ifdef CUST_EINT_MSDC1_INS_NUM
.flags = MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE | MSDC_HIGHSPEED | MSDC_UHS1 |MSDC_DDR ,
#else
.flags = MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_HIGHSPEED | MSDC_UHS1 |MSDC_DDR,
#endif
.dat0rddly = 0,
.dat1rddly = 0,
.dat2rddly = 0,
.dat3rddly = 0,
.dat4rddly = 0,
.dat5rddly = 0,
.dat6rddly = 0,
.dat7rddly = 0,
.datwrddly = 0,
.cmdrrddly = 0,
.cmdrddly = 0,
.host_function = MSDC_SD,
.boot = 0,
.cd_level = MSDC_CD_HIGH,
};
#endif
#endif
#if defined(CFG_DEV_MSDC2)
#if defined(CONFIG_MTK_WCN_CMB_SDIO_SLOT) && (CONFIG_MTK_WCN_CMB_SDIO_SLOT == 2)
/* MSDC2 settings for MT66xx combo connectivity chip */
struct msdc_hw msdc2_hw = {
.clk_src = MSDC_CLKSRC_200MHZ,
.cmd_edge = MSDC_SMPL_FALLING,
.rdata_edge = MSDC_SMPL_FALLING,
.wdata_edge = MSDC_SMPL_FALLING,
.clk_drv = 0,
.cmd_drv = 0,
.dat_drv = 0,
.data_pins = 4,
.data_offset = 0,
//MT6620 use External IRQ, wifi uses high speed. here wifi manage his own suspend and resume, does not support hot plug
.flags = MSDC_SDIO_FLAG,//MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE,
.dat0rddly = 0,
.dat1rddly = 0,
.dat2rddly = 0,
.dat3rddly = 0,
.dat4rddly = 0,
.dat5rddly = 0,
.dat6rddly = 0,
.dat7rddly = 0,
.datwrddly = 0,
.cmdrrddly = 0,
.cmdrddly = 0,
.host_function = MSDC_SDIO,
.boot = 0,
.request_sdio_eirq = mtk_wcn_cmb_sdio_request_eirq,
.enable_sdio_eirq = mtk_wcn_cmb_sdio_enable_eirq,
.disable_sdio_eirq = mtk_wcn_cmb_sdio_disable_eirq,
.register_pm = mtk_wcn_cmb_sdio_register_pm,
};
#else
#if 0
struct msdc_hw msdc2_hw = {
.clk_src = MSDC_CLKSRC_200MHZ,
.cmd_edge = MSDC_SMPL_FALLING,
.rdata_edge = MSDC_SMPL_FALLING,
.wdata_edge = MSDC_SMPL_FALLING,
.clk_drv = 3,
.cmd_drv = 2,
.dat_drv = 2,
.clk_drv_sd_18 = 4,
.cmd_drv_sd_18 = 3,
.dat_drv_sd_18 = 3,
.data_pins = 4,
.data_offset = 0,
.flags = MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE | MSDC_HIGHSPEED,
.dat0rddly = 0,
.dat1rddly = 0,
.dat2rddly = 0,
.dat3rddly = 0,
.dat4rddly = 0,
.dat5rddly = 0,
.dat6rddly = 0,
.dat7rddly = 0,
.datwrddly = 0,
.cmdrrddly = 0,
.cmdrddly = 0,
.host_function = MSDC_SD,
.boot = 0,
.cd_level = MSDC_CD_LOW,
};
#endif
#endif
#endif
#if defined(CFG_DEV_MSDC3)
#if defined(CONFIG_MTK_WCN_CMB_SDIO_SLOT) && (CONFIG_MTK_WCN_CMB_SDIO_SLOT == 3)
/* MSDC3 settings for MT66xx combo connectivity chip */
struct msdc_hw msdc3_hw = {
.clk_src = MSDC_CLKSRC_200MHZ,
.cmd_edge = MSDC_SMPL_FALLING,
.rdata_edge = MSDC_SMPL_FALLING,
.wdata_edge = MSDC_SMPL_FALLING,
.clk_drv = 0,
.cmd_drv = 0,
.dat_drv = 0,
.data_pins = 4,
.data_offset = 0,
//MT6620 use External IRQ, wifi uses high speed. here wifi manage his own suspend and resume, does not support hot plug
.flags = MSDC_SDIO_FLAG,//MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE,
.dat0rddly = 0,
.dat1rddly = 0,
.dat2rddly = 0,
.dat3rddly = 0,
.dat4rddly = 0,
.dat5rddly = 0,
.dat6rddly = 0,
.dat7rddly = 0,
.datwrddly = 0,
.cmdrrddly = 0,
.cmdrddly = 0,
.host_function = MSDC_SDIO,
.boot = 0,
.request_sdio_eirq = mtk_wcn_cmb_sdio_request_eirq,
.enable_sdio_eirq = mtk_wcn_cmb_sdio_enable_eirq,
.disable_sdio_eirq = mtk_wcn_cmb_sdio_disable_eirq,
.register_pm = mtk_wcn_cmb_sdio_register_pm,
};
#if 0
struct msdc_hw msdc3_hw = {
.clk_src = 1,
.cmd_edge = MSDC_SMPL_FALLING,
.data_edge = MSDC_SMPL_FALLING,
.clk_drv = 4,
.cmd_drv = 4,
.dat_drv = 4,
.data_pins = 4,
.data_offset = 0,
.flags = MSDC_SDCARD_FLAG,
.dat0rddly = 0,
.dat1rddly = 0,
.dat2rddly = 0,
.dat3rddly = 0,
.dat4rddly = 0,
.dat5rddly = 0,
.dat6rddly = 0,
.dat7rddly = 0,
.datwrddly = 0,
.cmdrrddly = 0,
.cmdrddly = 0,
};
#endif
#endif
#endif
#if defined(CFG_DEV_MSDC4)
#if defined(CONFIG_MTK_WCN_CMB_SDIO_SLOT) && (CONFIG_MTK_WCN_CMB_SDIO_SLOT == 4)
struct msdc_hw msdc4_hw = {
.clk_src = MSDC_CLKSRC_200MHZ,
.cmd_edge = MSDC_SMPL_FALLING,
.rdata_edge = MSDC_SMPL_FALLING,
.wdata_edge = MSDC_SMPL_FALLING,
.clk_drv = 0,
.cmd_drv = 0,
.dat_drv = 0,
.data_pins = 4,
.data_offset = 0,
//MT6620 use External IRQ, wifi uses high speed. here wifi manage his own suspend and resume, does not support hot plug
.flags = MSDC_SDIO_FLAG,//MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE,(this flag is for SD card)
.dat0rddly = 0,
.dat1rddly = 0,
.dat2rddly = 0,
.dat3rddly = 0,
.dat4rddly = 0,
.dat5rddly = 0,
.dat6rddly = 0,
.dat7rddly = 0,
.datwrddly = 0,
.cmdrrddly = 0,
.cmdrddly = 0,
.host_function = MSDC_SDIO,
.boot = 0,
.request_sdio_eirq = mtk_wcn_cmb_sdio_request_eirq,
.enable_sdio_eirq = mtk_wcn_cmb_sdio_enable_eirq,
.disable_sdio_eirq = mtk_wcn_cmb_sdio_disable_eirq,
.register_pm = mtk_wcn_cmb_sdio_register_pm,
};
#else
struct msdc_hw msdc4_hw = {
.clk_src = MSDC_CLKSRC_200MHZ,
.cmd_edge = MSDC_SMPL_FALLING,
.rdata_edge = MSDC_SMPL_FALLING,
.wdata_edge = MSDC_SMPL_FALLING,
.clk_drv = 1,
.cmd_drv = 0,
.dat_drv = 0,
.data_pins = 8,
.data_offset = 0,
.flags = MSDC_SYS_SUSPEND | MSDC_HIGHSPEED | MSDC_UHS1 |MSDC_DDR,
.dat0rddly = 0,
.dat1rddly = 0,
.dat2rddly = 0,
.dat3rddly = 0,
.dat4rddly = 0,
.dat5rddly = 0,
.dat6rddly = 0,
.dat7rddly = 0,
.datwrddly = 0,
.cmdrrddly = 0,
.cmdrddly = 0,
.host_function = MSDC_EMMC,
.boot = MSDC_BOOT_EN,
};
#endif
#endif
/* MT6575 NAND Driver */
#if defined(CONFIG_MTK_MTD_NAND)
struct mt6575_nand_host_hw mt6575_nand_hw = {
.nfi_bus_width = 8,
.nfi_access_timing = NFI_DEFAULT_ACCESS_TIMING,
.nfi_cs_num = NFI_CS_NUM,
.nand_sec_size = 512,
.nand_sec_shift = 9,
.nand_ecc_size = 2048,
.nand_ecc_bytes = 32,
.nand_ecc_mode = NAND_ECC_HW,
};
#endif
arch/arm/mach-mt8127/ford/core/logger_custom.h
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#ifndef __LOGGER_CUSTOM_H
#define __LOGGER_CUSTOM_H
#include <generated/autoconf.h>
#define __MAIN_BUF_SIZE 64*1024
#define __EVENTS_BUF_SIZE 256*1024
#define __RADIO_BUF_SIZE 64*1024
#define __SYSTEM_BUF_SIZE 64*1024
#endif /* __LOGGER_CUSTOM_H */
arch/arm/mach-mt8127/ford/dct/dct/Makefile
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+4
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include $(srctree)/drivers/misc/mediatek/Makefile.custom
obj-y := pmic_drv.o
arch/arm/mach-mt8127/ford/dct/dct/codegen.dws
Executable
BIN
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arch/arm/mach-mt8127/ford/dct/dct/cust_adc.h
+15
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/*
* Generated by MTK SP Drv_CodeGen Version 03.13.6 for MT8127. Copyright MediaTek Inc. (C) 2013.
* Thu Jan 29 20:42:51 2015
* Do Not Modify the File.
*/
#ifndef __CUST_AUXADC_TOOL_H
#define __CUST_AUXADC_TOOL_H
#endif //_CUST_AUXADC_TOOL_H
arch/arm/mach-mt8127/ford/dct/dct/cust_eint.h
Executable
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/*
* Generated by MTK SP DrvGen Version 03.13.6 for MT8127. Copyright MediaTek Inc. (C) 2013.
* Tue Apr 07 23:26:37 2015
* Do Not Modify the File.
*/
#ifndef __CUST_EINTH
#define __CUST_EINTH
#ifdef __cplusplus
extern "C" {
#endif
#define CUST_EINTF_TRIGGER_RISING 1 //High Polarity and Edge Sensitive
#define CUST_EINTF_TRIGGER_FALLING 2 //Low Polarity and Edge Sensitive
#define CUST_EINTF_TRIGGER_HIGH 4 //High Polarity and Level Sensitive
#define CUST_EINTF_TRIGGER_LOW 8 //Low Polarity and Level Sensitive
#define CUST_EINT_DEBOUNCE_DISABLE 0
#define CUST_EINT_DEBOUNCE_ENABLE 1
//////////////////////////////////////////////////////////////////////////////
#define CUST_EINT_KPD_SLIDE_NUM 0
#define CUST_EINT_KPD_SLIDE_DEBOUNCE_CN 0
#define CUST_EINT_KPD_SLIDE_TYPE CUST_EINTF_TRIGGER_LOW
#define CUST_EINT_KPD_SLIDE_DEBOUNCE_EN CUST_EINT_DEBOUNCE_DISABLE
#define CUST_EINT_GSE_1_NUM 1
#define CUST_EINT_GSE_1_DEBOUNCE_CN 0
#define CUST_EINT_GSE_1_TYPE CUST_EINTF_TRIGGER_HIGH
#define CUST_EINT_GSE_1_DEBOUNCE_EN CUST_EINT_DEBOUNCE_DISABLE
#define CUST_EINT_ACCDET_NUM 4
#define CUST_EINT_ACCDET_DEBOUNCE_CN 256
#define CUST_EINT_ACCDET_TYPE CUST_EINTF_TRIGGER_LOW
#define CUST_EINT_ACCDET_DEBOUNCE_EN CUST_EINT_DEBOUNCE_ENABLE
#define CUST_EINT_MSDC1_INS_NUM 6
#define CUST_EINT_MSDC1_INS_DEBOUNCE_CN 0
#define CUST_EINT_MSDC1_INS_TYPE CUST_EINTF_TRIGGER_HIGH
#define CUST_EINT_MSDC1_INS_DEBOUNCE_EN CUST_EINT_DEBOUNCE_DISABLE
#define CUST_EINT_TOUCH_PANEL_NUM 7
#define CUST_EINT_TOUCH_PANEL_DEBOUNCE_CN 1
#define CUST_EINT_TOUCH_PANEL_TYPE CUST_EINTF_TRIGGER_FALLING
#define CUST_EINT_TOUCH_PANEL_DEBOUNCE_EN CUST_EINT_DEBOUNCE_DISABLE
#define CUST_EINT_GSE_2_NUM 10
#define CUST_EINT_GSE_2_DEBOUNCE_CN 0
#define CUST_EINT_GSE_2_TYPE CUST_EINTF_TRIGGER_HIGH
#define CUST_EINT_GSE_2_DEBOUNCE_EN CUST_EINT_DEBOUNCE_DISABLE
#define CUST_EINT_MSE_NUM 11
#define CUST_EINT_MSE_DEBOUNCE_CN 0
#define CUST_EINT_MSE_TYPE CUST_EINTF_TRIGGER_LOW
#define CUST_EINT_MSE_DEBOUNCE_EN CUST_EINT_DEBOUNCE_DISABLE
#define CUST_EINT_MT6323_PMIC_NUM 24
#define CUST_EINT_MT6323_PMIC_DEBOUNCE_CN 1
#define CUST_EINT_MT6323_PMIC_TYPE CUST_EINTF_TRIGGER_HIGH
#define CUST_EINT_MT6323_PMIC_DEBOUNCE_EN CUST_EINT_DEBOUNCE_ENABLE
//////////////////////////////////////////////////////////////////////////////
#ifdef __cplusplus
}
#endif
#endif //_CUST_EINT_H
arch/arm/mach-mt8127/ford/dct/dct/cust_eint_ext.h
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/*
* Generated by MTK SP DrvGen Version 03.13.6 for MT8127. Copyright MediaTek Inc. (C) 2013.
* Thu Jan 29 20:42:51 2015
* Do Not Modify the File.
*/
#ifndef __CUST_EINTH
#define __CUST_EINTH
#ifdef __cplusplus
extern "C" {
#endif
#define CUST_EINTF_TRIGGER_RISING 1 //High Polarity and Edge Sensitive
#define CUST_EINTF_TRIGGER_FALLING 2 //Low Polarity and Edge Sensitive
#define CUST_EINTF_TRIGGER_HIGH 4 //High Polarity and Level Sensitive
#define CUST_EINTF_TRIGGER_LOW 8 //Low Polarity and Level Sensitive
#define CUST_EINT_DEBOUNCE_DISABLE 0
#define CUST_EINT_DEBOUNCE_ENABLE 1
//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
#ifdef __cplusplus
}
#endif
#endif //_CUST_EINT__EXT_H
arch/arm/mach-mt8127/ford/dct/dct/cust_gpio_boot.h
Executable
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arch/arm/mach-mt8127/ford/dct/dct/cust_gpio_usage.h
Executable
+143
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/*
* Generated by MTK SP Drv_CodeGen Version 03.13.6 for MT8127. Copyright MediaTek Inc. (C) 2013.
* Thu Jan 29 20:42:51 2015
* Do Not Modify the File.
*/
#ifndef __CUST_GPIO_USAGE_H__
#define __CUST_GPIO_USAGE_H__
#define GPIO_PMIC_EINT_PIN (GPIO2 | 0x80000000)
#define GPIO_PMIC_EINT_PIN_M_GPIO GPIO_MODE_00
#define GPIO_PMIC_EINT_PIN_M_EINT GPIO_PMIC_EINT_PIN_M_GPIO
#define GPIO_AUD_CLK_MOSI_PIN (GPIO7 | 0x80000000)
#define GPIO_AUD_CLK_MOSI_PIN_M_GPIO GPIO_MODE_00
#define GPIO_AUD_CLK_MOSI_PIN_M_CLK GPIO_MODE_01
#define GPIO_AUD_DAT_MISO_PIN (GPIO8 | 0x80000000)
#define GPIO_AUD_DAT_MISO_PIN_M_GPIO GPIO_MODE_00
#define GPIO_AUD_DAT_MISO_PIN_M_AUD_MISO GPIO_MODE_01
#define GPIO_AUD_DAT_MOSI_PIN (GPIO9 | 0x80000000)
#define GPIO_AUD_DAT_MOSI_PIN_M_GPIO GPIO_MODE_00
#define GPIO_AUD_DAT_MOSI_PIN_M_AUD_MOSI GPIO_MODE_01
#define GPIO_QWERTYSLIDE_EINT_PIN (GPIO22 | 0x80000000)
#define GPIO_QWERTYSLIDE_EINT_PIN_M_GPIO GPIO_MODE_00
#define GPIO_QWERTYSLIDE_EINT_PIN_M_PWM GPIO_MODE_01
#define GPIO_QWERTYSLIDE_EINT_PIN_M_EINT GPIO_QWERTYSLIDE_EINT_PIN_M_GPIO
#define GPIO_ACCDET_EINT_PIN (GPIO26 | 0x80000000)
#define GPIO_ACCDET_EINT_PIN_M_GPIO GPIO_MODE_00
#define GPIO_ACCDET_EINT_PIN_M_CLK GPIO_MODE_01
#define GPIO_ACCDET_EINT_PIN_M_EINT GPIO_ACCDET_EINT_PIN_M_GPIO
#define GPIO_ACCDET_EINT_PIN_CLK CLK_OUT2
#define GPIO_ACCDET_EINT_PIN_FREQ GPIO_CLKSRC_NONE
#define GPIO_OTG_DRVVBUS_PIN (GPIO27 | 0x80000000)
#define GPIO_OTG_DRVVBUS_PIN_M_GPIO GPIO_MODE_00
#define GPIO_OTG_DRVVBUS_PIN_M_KCOL GPIO_MODE_06
#define GPIO_CTP_EINT_PIN (GPIO29 | 0x80000000)
#define GPIO_CTP_EINT_PIN_M_GPIO GPIO_MODE_00
#define GPIO_CTP_EINT_PIN_M_EINT GPIO_CTP_EINT_PIN_M_GPIO
#define GPIO_SPEAKER_EN_PIN (GPIO30 | 0x80000000)
#define GPIO_SPEAKER_EN_PIN_M_GPIO GPIO_MODE_00
#define GPIO_SPEAKER_EN_PIN_M_CLK GPIO_MODE_02
#define GPIO_SPEAKER_EN_PIN_CLK CLK_OUT3
#define GPIO_SPEAKER_EN_PIN_FREQ GPIO_CLKSRC_NONE
#define GPIO_KPD_KCOL0_PIN (GPIO36 | 0x80000000)
#define GPIO_KPD_KCOL0_PIN_M_GPIO GPIO_MODE_00
#define GPIO_KPD_KCOL0_PIN_M_KCOL GPIO_MODE_01
#define GPIO_KPD_KCOL1_PIN (GPIO37 | 0x80000000)
#define GPIO_KPD_KCOL1_PIN_M_GPIO GPIO_MODE_00
#define GPIO_KPD_KCOL1_PIN_M_KCOL GPIO_MODE_01
#define GPIO_OTG_IDDIG_EINT_PIN (GPIO38 | 0x80000000)
#define GPIO_OTG_IDDIG_EINT_PIN_M_GPIO GPIO_MODE_00
#define GPIO_OTG_IDDIG_EINT_PIN_M_KCOL GPIO_MODE_01
#define GPIO_OTG_IDDIG_EINT_PIN_M_IDDIG GPIO_MODE_02
#define GPIO_CTP_RST_PIN (GPIO45 | 0x80000000)
#define GPIO_CTP_RST_PIN_M_GPIO GPIO_MODE_00
#define GPIO_CAMERA_CMRST_PIN (GPIO53 | 0x80000000)
#define GPIO_CAMERA_CMRST_PIN_M_GPIO GPIO_MODE_00
#define GPIO_CAMERA_CMPDN1_PIN (GPIO54 | 0x80000000)
#define GPIO_CAMERA_CMPDN1_PIN_M_GPIO GPIO_MODE_00
#define GPIO_CAMERA_CMRST1_PIN (GPIO55 | 0x80000000)
#define GPIO_CAMERA_CMRST1_PIN_M_GPIO GPIO_MODE_00
#define GPIO_CAMERA_CMPDN_PIN (GPIO56 | 0x80000000)
#define GPIO_CAMERA_CMPDN_PIN_M_GPIO GPIO_MODE_00
#define GPIO_I2C1_SDA_PIN (GPIO57 | 0x80000000)
#define GPIO_I2C1_SDA_PIN_M_GPIO GPIO_MODE_00
#define GPIO_I2C1_SDA_PIN_M_SDA GPIO_MODE_01
#define GPIO_I2C1_SCA_PIN (GPIO58 | 0x80000000)
#define GPIO_I2C1_SCA_PIN_M_GPIO GPIO_MODE_00
#define GPIO_I2C1_SCA_PIN_M_SCL GPIO_MODE_01
#define GPIO_I2C0_SDA_PIN (GPIO75 | 0x80000000)
#define GPIO_I2C0_SDA_PIN_M_GPIO GPIO_MODE_00
#define GPIO_I2C0_SDA_PIN_M_SDA GPIO_MODE_01
#define GPIO_I2C0_SCA_PIN (GPIO76 | 0x80000000)
#define GPIO_I2C0_SCA_PIN_M_GPIO GPIO_MODE_00
#define GPIO_I2C0_SCA_PIN_M_SCL GPIO_MODE_01
#define GPIO_I2C2_SDA_PIN (GPIO77 | 0x80000000)
#define GPIO_I2C2_SDA_PIN_M_GPIO GPIO_MODE_00
#define GPIO_I2C2_SDA_PIN_M_PWM GPIO_MODE_02
#define GPIO_I2C2_SDA_PIN_M_SDA GPIO_MODE_01
#define GPIO_I2C2_SCA_PIN (GPIO78 | 0x80000000)
#define GPIO_I2C2_SCA_PIN_M_GPIO GPIO_MODE_00
#define GPIO_I2C2_SCA_PIN_M_PWM GPIO_MODE_02
#define GPIO_I2C2_SCA_PIN_M_SCL GPIO_MODE_01
#define GPIO_UART_URXD1_PIN (GPIO79 | 0x80000000)
#define GPIO_UART_URXD1_PIN_M_GPIO GPIO_MODE_00
#define GPIO_UART_URXD1_PIN_M_URXD GPIO_MODE_01
#define GPIO_UART_URXD1_PIN_M_UTXD GPIO_MODE_02
#define GPIO_UART_UTXD1_PIN (GPIO80 | 0x80000000)
#define GPIO_UART_UTXD1_PIN_M_GPIO GPIO_MODE_00
#define GPIO_UART_UTXD1_PIN_M_UTXD GPIO_MODE_01
#define GPIO_UART_UTXD1_PIN_M_URXD GPIO_MODE_02
#define GPIO_LCM_PWR (GPIO83 | 0x80000000)
#define GPIO_LCM_PWR_M_GPIO GPIO_MODE_00
#define GPIO_LCM_STB (GPIO88 | 0x80000000)
#define GPIO_LCM_STB_M_GPIO GPIO_MODE_00
#define GPIO_LCM_STB_M_PWM GPIO_MODE_03
#define GPIO_LCM_STB_M_PWM GPIO_MODE_06
#define GPIO_LCM_RST (GPIO89 | 0x80000000)
#define GPIO_LCM_RST_M_GPIO GPIO_MODE_00
#define GPIO_LCM_RST_M_PWM GPIO_MODE_06
/*Output for default variable names*/
/*@XXX_XX_PIN in gpio.cmp */
/*Output for default variable names*/
/*@XXX_XX_PIN in gpio.cmp */
#endif /* __CUST_GPIO_USAGE_H__ */
arch/arm/mach-mt8127/ford/dct/dct/cust_kpd.h
+105
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@@ -0,0 +1,105 @@
/*
* Generated by MTK SP Drv_CodeGen Version 03.13.6 for MT8127. Copyright MediaTek Inc. (C) 2013.
* Thu Jan 29 20:42:51 2015
* Do Not Modify the File.
*/
#ifndef _CUST_KPD_H_
#define _CUST_KPD_H_
#include <linux/input.h>
#include <cust_eint.h>
#define KPD_YES 1
#define KPD_NO 0
/* available keys (Linux keycodes) */
#define KEY_CALL KEY_SEND
#define KEY_ENDCALL KEY_END
#undef KEY_OK
#define KEY_OK KEY_REPLY /* DPAD_CENTER */
#define KEY_FOCUS KEY_HP
#define KEY_AT KEY_EMAIL
#define KEY_POUND 228 //KEY_KBDILLUMTOGGLE
#define KEY_STAR 227 //KEY_SWITCHVIDEOMODE
#define KEY_DEL KEY_BACKSPACE
#define KEY_SYM KEY_COMPOSE
/* KEY_HOME */
/* KEY_BACK */
/* KEY_VOLUMEDOWN */
/* KEY_VOLUMEUP */
/* KEY_MUTE */
/* KEY_MENU */
/* KEY_UP */
/* KEY_DOWN */
/* KEY_LEFT */
/* KEY_RIGHT */
/* KEY_CAMERA */
/* KEY_POWER */
/* KEY_TAB */
/* KEY_ENTER */
/* KEY_LEFTSHIFT */
/* KEY_COMMA */
/* KEY_DOT */ /* PERIOD */
/* KEY_SLASH */
/* KEY_LEFTALT */
/* KEY_RIGHTALT */
/* KEY_SPACE */
/* KEY_SEARCH */
/* KEY_0 ~ KEY_9 */
/* KEY_A ~ KEY_Z */
/*
* Power key's HW keycodes are 8, 17, 26, 35, 44, 53, 62, 71. Only [8] works
* for Power key in Keypad driver, so we set KEY_ENDCALL in [8] because
* EndCall key is Power key in Android. If KPD_PWRKEY_USE_EINT is YES, these
* eight keycodes will not work for Power key.
*/
#define KPD_KEY_DEBOUNCE 1024 /* (val / 32) ms */
#define KPD_PWRKEY_MAP KEY_POWER
#define MTK_PMIC_PWR_KEY 8
/* HW keycode [0 ~ 71] -> Linux keycode */
#define KPD_INIT_KEYMAP() \
{ \
[0] = KEY_VOLUMEUP, \
[1] = KEY_VOLUMEDOWN, \
}
/*****************************************************************/
/*******************Preload Customation***************************/
/*****************************************************************/
#define KPD_PWRKEY_EINT_GPIO GPIO0
#define KPD_PWRKEY_GPIO_DIN 0
#define KPD_DL_KEY1 0 /* KEY_VOLUMEUP */
#define KPD_DL_KEY2 1 /* KEY_VOLUMEDOWN */
#define KPD_DL_KEY3 8 /* KEY_POWER */
/*****************************************************************/
/*******************Uboot Customation***************************/
/*****************************************************************/
#define MT65XX_RECOVERY_KEY 0 /* KEY_VOLUMEUP */
#define MT65XX_FACTORY_KEY 1 /* KEY_VOLUMEDOWN */
/*****************************************************************/
/*******************factory Customation***************************/
/*****************************************************************/
#define KEYS_PWRKEY_MAP { KEY_POWER, "Power" }
#define DEFINE_KEYS_KEYMAP(x) \
struct key x[] = { \
KEYS_PWRKEY_MAP, \
{ KEY_VOLUMEUP, "VLUp" }, \
{ KEY_VOLUMEDOWN, "VLDown" }, \
}
#define CUST_KEY_UP KEY_VOLUMEUP
#define CUST_KEY_VOLUP KEY_VOLUMEUP
#define CUST_KEY_DOWN KEY_VOLUMEDOWN
#define CUST_KEY_VOLDOWN KEY_VOLUMEDOWN
#define CUST_KEY_CONFIRM KEY_VOLUMEUP
/*****************************************************************/
/*******************recovery Customation****************************/
/*****************************************************************/
#endif
arch/arm/mach-mt8127/ford/dct/dct/cust_power.h
+9
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@@ -0,0 +1,9 @@
/*
* Generated by MTK SP DrvGen Version 03.13.6 for MT8127. Copyright MediaTek Inc. (C) 2013.
* Thu Jan 29 20:42:51 2015
* Do Not Modify the File.
*/
#define GPIO_DVDD28_DPI GPIO_VIO28
arch/arm/mach-mt8127/ford/dct/dct/pmic_drv.c
+16
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@@ -0,0 +1,16 @@
/*
* Generated by MTK SP Drv_CodeGen Version 03.13.6 for MT8127. Copyright MediaTek Inc. (C) 2013.
* Thu Jan 29 20:42:51 2015
* Do Not Modify the File.
*/
#include "pmic_drv.h"
//For PMIC driver use
arch/arm/mach-mt8127/ford/dct/dct/pmic_drv.h
+30
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@@ -0,0 +1,30 @@
/*
* Generated by MTK SP Drv_CodeGen Version 03.13.6 for MT8127. Copyright MediaTek Inc. (C) 2013.
* Thu Jan 29 20:42:51 2015
* Do Not Modify the File.
*/
#include <mach/upmu_sw.h>
//****for customer use*******//
//PMIC default enable/disable result
//PMIC mode select
typedef enum
{
BY_ENABLE = 0,
BY_SRCLKEN = 1
}MODE_sel_enum;
////For Common use
//For PMIC driver use
arch/arm/mach-mt8127/ford/dct/dct_austin/Makefile
Executable
+4
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@@ -0,0 +1,4 @@
include $(srctree)/drivers/misc/mediatek/Makefile.custom
obj-y := pmic_drv.o
arch/arm/mach-mt8127/ford/dct/dct_austin/codegen.dws
Executable
BIN
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Binary file not shown.
arch/arm/mach-mt8127/ford/dct/dct_austin/cust_adc.h
Executable
+15
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@@ -0,0 +1,15 @@
/*
* Generated by MTK SP Drv_CodeGen Version 03.13.6 for MT8127. Copyright MediaTek Inc. (C) 2013.
* Thu Jan 29 20:42:51 2015
* Do Not Modify the File.
*/
#ifndef __CUST_AUXADC_TOOL_H
#define __CUST_AUXADC_TOOL_H
#endif //_CUST_AUXADC_TOOL_H
arch/arm/mach-mt8127/ford/dct/dct_austin/cust_eint.h
Executable
+69
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@@ -0,0 +1,69 @@
/*
* Generated by MTK SP DrvGen Version 03.13.6 for MT8127. Copyright MediaTek Inc. (C) 2013.
* Tue Apr 07 23:26:37 2015
* Do Not Modify the File.
*/
#ifndef __CUST_EINTH
#define __CUST_EINTH
#ifdef __cplusplus
extern "C" {
#endif
#define CUST_EINTF_TRIGGER_RISING 1 //High Polarity and Edge Sensitive
#define CUST_EINTF_TRIGGER_FALLING 2 //Low Polarity and Edge Sensitive
#define CUST_EINTF_TRIGGER_HIGH 4 //High Polarity and Level Sensitive
#define CUST_EINTF_TRIGGER_LOW 8 //Low Polarity and Level Sensitive
#define CUST_EINT_DEBOUNCE_DISABLE 0
#define CUST_EINT_DEBOUNCE_ENABLE 1
//////////////////////////////////////////////////////////////////////////////
#define CUST_EINT_KPD_SLIDE_NUM 0
#define CUST_EINT_KPD_SLIDE_DEBOUNCE_CN 0
#define CUST_EINT_KPD_SLIDE_TYPE CUST_EINTF_TRIGGER_LOW
#define CUST_EINT_KPD_SLIDE_DEBOUNCE_EN CUST_EINT_DEBOUNCE_DISABLE
#define CUST_EINT_GSE_1_NUM 1
#define CUST_EINT_GSE_1_DEBOUNCE_CN 0
#define CUST_EINT_GSE_1_TYPE CUST_EINTF_TRIGGER_HIGH
#define CUST_EINT_GSE_1_DEBOUNCE_EN CUST_EINT_DEBOUNCE_DISABLE
#define CUST_EINT_ACCDET_NUM 4
#define CUST_EINT_ACCDET_DEBOUNCE_CN 256
#define CUST_EINT_ACCDET_TYPE CUST_EINTF_TRIGGER_LOW
#define CUST_EINT_ACCDET_DEBOUNCE_EN CUST_EINT_DEBOUNCE_ENABLE
#define CUST_EINT_MSDC1_INS_NUM 6
#define CUST_EINT_MSDC1_INS_DEBOUNCE_CN 0
#define CUST_EINT_MSDC1_INS_TYPE CUST_EINTF_TRIGGER_HIGH
#define CUST_EINT_MSDC1_INS_DEBOUNCE_EN CUST_EINT_DEBOUNCE_DISABLE
#define CUST_EINT_TOUCH_PANEL_NUM 7
#define CUST_EINT_TOUCH_PANEL_DEBOUNCE_CN 1
#define CUST_EINT_TOUCH_PANEL_TYPE CUST_EINTF_TRIGGER_FALLING
#define CUST_EINT_TOUCH_PANEL_DEBOUNCE_EN CUST_EINT_DEBOUNCE_DISABLE
#define CUST_EINT_GSE_2_NUM 10
#define CUST_EINT_GSE_2_DEBOUNCE_CN 0
#define CUST_EINT_GSE_2_TYPE CUST_EINTF_TRIGGER_HIGH
#define CUST_EINT_GSE_2_DEBOUNCE_EN CUST_EINT_DEBOUNCE_DISABLE
#define CUST_EINT_MSE_NUM 11
#define CUST_EINT_MSE_DEBOUNCE_CN 0
#define CUST_EINT_MSE_TYPE CUST_EINTF_TRIGGER_LOW
#define CUST_EINT_MSE_DEBOUNCE_EN CUST_EINT_DEBOUNCE_DISABLE
#define CUST_EINT_MT6323_PMIC_NUM 24
#define CUST_EINT_MT6323_PMIC_DEBOUNCE_CN 1
#define CUST_EINT_MT6323_PMIC_TYPE CUST_EINTF_TRIGGER_HIGH
#define CUST_EINT_MT6323_PMIC_DEBOUNCE_EN CUST_EINT_DEBOUNCE_ENABLE
//////////////////////////////////////////////////////////////////////////////
#ifdef __cplusplus
}
#endif
#endif //_CUST_EINT_H
arch/arm/mach-mt8127/ford/dct/dct_austin/cust_eint_ext.h
Executable
+34
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@@ -0,0 +1,34 @@
/*
* Generated by MTK SP DrvGen Version 03.13.6 for MT8127. Copyright MediaTek Inc. (C) 2013.
* Thu Jan 29 20:42:51 2015
* Do Not Modify the File.
*/
#ifndef __CUST_EINTH
#define __CUST_EINTH
#ifdef __cplusplus
extern "C" {
#endif
#define CUST_EINTF_TRIGGER_RISING 1 //High Polarity and Edge Sensitive
#define CUST_EINTF_TRIGGER_FALLING 2 //Low Polarity and Edge Sensitive
#define CUST_EINTF_TRIGGER_HIGH 4 //High Polarity and Level Sensitive
#define CUST_EINTF_TRIGGER_LOW 8 //Low Polarity and Level Sensitive
#define CUST_EINT_DEBOUNCE_DISABLE 0
#define CUST_EINT_DEBOUNCE_ENABLE 1
//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
#ifdef __cplusplus
}
#endif
#endif //_CUST_EINT__EXT_H
arch/arm/mach-mt8127/ford/dct/dct_austin/cust_gpio_boot.h
Executable
+1348
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File diff suppressed because it is too large Load Diff
arch/arm/mach-mt8127/ford/dct/dct_austin/cust_gpio_usage.h
Executable
+138
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@@ -0,0 +1,138 @@
/*
* Generated by MTK SP Drv_CodeGen Version 03.13.6 for MT8127. Copyright MediaTek Inc. (C) 2013.
* Thu Jan 29 20:42:51 2015
* Do Not Modify the File.
*/
#ifndef __CUST_GPIO_USAGE_H__
#define __CUST_GPIO_USAGE_H__
#define GPIO_PMIC_EINT_PIN (GPIO2 | 0x80000000)
#define GPIO_PMIC_EINT_PIN_M_GPIO GPIO_MODE_00
#define GPIO_PMIC_EINT_PIN_M_EINT GPIO_PMIC_EINT_PIN_M_GPIO
#define GPIO_AUD_CLK_MOSI_PIN (GPIO7 | 0x80000000)
#define GPIO_AUD_CLK_MOSI_PIN_M_GPIO GPIO_MODE_00
#define GPIO_AUD_CLK_MOSI_PIN_M_CLK GPIO_MODE_01
#define GPIO_AUD_DAT_MISO_PIN (GPIO8 | 0x80000000)
#define GPIO_AUD_DAT_MISO_PIN_M_GPIO GPIO_MODE_00
#define GPIO_AUD_DAT_MISO_PIN_M_AUD_MISO GPIO_MODE_01
#define GPIO_AUD_DAT_MOSI_PIN (GPIO9 | 0x80000000)
#define GPIO_AUD_DAT_MOSI_PIN_M_GPIO GPIO_MODE_00
#define GPIO_AUD_DAT_MOSI_PIN_M_AUD_MOSI GPIO_MODE_01
#define GPIO_QWERTYSLIDE_EINT_PIN (GPIO22 | 0x80000000)
#define GPIO_QWERTYSLIDE_EINT_PIN_M_GPIO GPIO_MODE_00
#define GPIO_QWERTYSLIDE_EINT_PIN_M_PWM GPIO_MODE_01
#define GPIO_QWERTYSLIDE_EINT_PIN_M_EINT GPIO_QWERTYSLIDE_EINT_PIN_M_GPIO
#define GPIO_ACCDET_EINT_PIN (GPIO26 | 0x80000000)
#define GPIO_ACCDET_EINT_PIN_M_GPIO GPIO_MODE_00
#define GPIO_ACCDET_EINT_PIN_M_CLK GPIO_MODE_01
#define GPIO_ACCDET_EINT_PIN_M_EINT GPIO_ACCDET_EINT_PIN_M_GPIO
#define GPIO_ACCDET_EINT_PIN_CLK CLK_OUT2
#define GPIO_ACCDET_EINT_PIN_FREQ GPIO_CLKSRC_NONE
#define GPIO_OTG_DRVVBUS_PIN (GPIO27 | 0x80000000)
#define GPIO_OTG_DRVVBUS_PIN_M_GPIO GPIO_MODE_00
#define GPIO_OTG_DRVVBUS_PIN_M_KCOL GPIO_MODE_06
#define GPIO_CTP_EINT_PIN (GPIO29 | 0x80000000)
#define GPIO_CTP_EINT_PIN_M_GPIO GPIO_MODE_00
#define GPIO_CTP_EINT_PIN_M_EINT GPIO_CTP_EINT_PIN_M_GPIO
#define GPIO_SPEAKER_EN_PIN (GPIO30 | 0x80000000)
#define GPIO_SPEAKER_EN_PIN_M_GPIO GPIO_MODE_00
#define GPIO_SPEAKER_EN_PIN_M_CLK GPIO_MODE_02
#define GPIO_SPEAKER_EN_PIN_CLK CLK_OUT3
#define GPIO_SPEAKER_EN_PIN_FREQ GPIO_CLKSRC_NONE
#define GPIO_KPD_KCOL0_PIN (GPIO36 | 0x80000000)
#define GPIO_KPD_KCOL0_PIN_M_GPIO GPIO_MODE_00
#define GPIO_KPD_KCOL0_PIN_M_KCOL GPIO_MODE_01
#define GPIO_KPD_KCOL1_PIN (GPIO37 | 0x80000000)
#define GPIO_KPD_KCOL1_PIN_M_GPIO GPIO_MODE_00
#define GPIO_KPD_KCOL1_PIN_M_KCOL GPIO_MODE_01
#define GPIO_OTG_IDDIG_EINT_PIN (GPIO38 | 0x80000000)
#define GPIO_OTG_IDDIG_EINT_PIN_M_GPIO GPIO_MODE_00
#define GPIO_OTG_IDDIG_EINT_PIN_M_KCOL GPIO_MODE_01
#define GPIO_OTG_IDDIG_EINT_PIN_M_IDDIG GPIO_MODE_02
#define GPIO_CTP_RST_PIN (GPIO45 | 0x80000000)
#define GPIO_CTP_RST_PIN_M_GPIO GPIO_MODE_00
#define GPIO_CAMERA_CMRST_PIN (GPIO53 | 0x80000000)
#define GPIO_CAMERA_CMRST_PIN_M_GPIO GPIO_MODE_00
#define GPIO_CAMERA_CMPDN1_PIN (GPIO54 | 0x80000000)
#define GPIO_CAMERA_CMPDN1_PIN_M_GPIO GPIO_MODE_00
#define GPIO_CAMERA_CMRST1_PIN (GPIO55 | 0x80000000)
#define GPIO_CAMERA_CMRST1_PIN_M_GPIO GPIO_MODE_00
#define GPIO_CAMERA_CMPDN_PIN (GPIO56 | 0x80000000)
#define GPIO_CAMERA_CMPDN_PIN_M_GPIO GPIO_MODE_00
#define GPIO_I2C1_SDA_PIN (GPIO57 | 0x80000000)
#define GPIO_I2C1_SDA_PIN_M_GPIO GPIO_MODE_00
#define GPIO_I2C1_SDA_PIN_M_SDA GPIO_MODE_01
#define GPIO_I2C1_SCA_PIN (GPIO58 | 0x80000000)
#define GPIO_I2C1_SCA_PIN_M_GPIO GPIO_MODE_00
#define GPIO_I2C1_SCA_PIN_M_SCL GPIO_MODE_01
#define GPIO_I2C0_SDA_PIN (GPIO75 | 0x80000000)
#define GPIO_I2C0_SDA_PIN_M_GPIO GPIO_MODE_00
#define GPIO_I2C0_SDA_PIN_M_SDA GPIO_MODE_01
#define GPIO_I2C0_SCA_PIN (GPIO76 | 0x80000000)
#define GPIO_I2C0_SCA_PIN_M_GPIO GPIO_MODE_00
#define GPIO_I2C0_SCA_PIN_M_SCL GPIO_MODE_01
#define GPIO_I2C2_SDA_PIN (GPIO77 | 0x80000000)
#define GPIO_I2C2_SDA_PIN_M_GPIO GPIO_MODE_00
#define GPIO_I2C2_SDA_PIN_M_PWM GPIO_MODE_02
#define GPIO_I2C2_SDA_PIN_M_SDA GPIO_MODE_01
#define GPIO_I2C2_SCA_PIN (GPIO78 | 0x80000000)
#define GPIO_I2C2_SCA_PIN_M_GPIO GPIO_MODE_00
#define GPIO_I2C2_SCA_PIN_M_PWM GPIO_MODE_02
#define GPIO_I2C2_SCA_PIN_M_SCL GPIO_MODE_01
#define GPIO_UART_URXD1_PIN (GPIO79 | 0x80000000)
#define GPIO_UART_URXD1_PIN_M_GPIO GPIO_MODE_00
#define GPIO_UART_URXD1_PIN_M_URXD GPIO_MODE_01
#define GPIO_UART_URXD1_PIN_M_UTXD GPIO_MODE_02
#define GPIO_UART_UTXD1_PIN (GPIO80 | 0x80000000)
#define GPIO_UART_UTXD1_PIN_M_GPIO GPIO_MODE_00
#define GPIO_UART_UTXD1_PIN_M_UTXD GPIO_MODE_01
#define GPIO_UART_UTXD1_PIN_M_URXD GPIO_MODE_02
#define GPIO_LCM_PWR (GPIO83 | 0x80000000)
#define GPIO_LCM_PWR_M_GPIO GPIO_MODE_00
#define GPIO_LCM_RST (GPIO89 | 0x80000000)
#define GPIO_LCM_RST_M_GPIO GPIO_MODE_00
#define GPIO_LCM_RST_M_PWM GPIO_MODE_06
/*Output for default variable names*/
/*@XXX_XX_PIN in gpio.cmp */
/*Output for default variable names*/
/*@XXX_XX_PIN in gpio.cmp */
#endif /* __CUST_GPIO_USAGE_H__ */
arch/arm/mach-mt8127/ford/dct/dct_austin/cust_kpd.h
Executable
+105
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@@ -0,0 +1,105 @@
/*
* Generated by MTK SP Drv_CodeGen Version 03.13.6 for MT8127. Copyright MediaTek Inc. (C) 2013.
* Thu Jan 29 20:42:51 2015
* Do Not Modify the File.
*/
#ifndef _CUST_KPD_H_
#define _CUST_KPD_H_
#include <linux/input.h>
#include <cust_eint.h>
#define KPD_YES 1
#define KPD_NO 0
/* available keys (Linux keycodes) */
#define KEY_CALL KEY_SEND
#define KEY_ENDCALL KEY_END
#undef KEY_OK
#define KEY_OK KEY_REPLY /* DPAD_CENTER */
#define KEY_FOCUS KEY_HP
#define KEY_AT KEY_EMAIL
#define KEY_POUND 228 //KEY_KBDILLUMTOGGLE
#define KEY_STAR 227 //KEY_SWITCHVIDEOMODE
#define KEY_DEL KEY_BACKSPACE
#define KEY_SYM KEY_COMPOSE
/* KEY_HOME */
/* KEY_BACK */
/* KEY_VOLUMEDOWN */
/* KEY_VOLUMEUP */
/* KEY_MUTE */
/* KEY_MENU */
/* KEY_UP */
/* KEY_DOWN */
/* KEY_LEFT */
/* KEY_RIGHT */
/* KEY_CAMERA */
/* KEY_POWER */
/* KEY_TAB */
/* KEY_ENTER */
/* KEY_LEFTSHIFT */
/* KEY_COMMA */
/* KEY_DOT */ /* PERIOD */
/* KEY_SLASH */
/* KEY_LEFTALT */
/* KEY_RIGHTALT */
/* KEY_SPACE */
/* KEY_SEARCH */
/* KEY_0 ~ KEY_9 */
/* KEY_A ~ KEY_Z */
/*
* Power key's HW keycodes are 8, 17, 26, 35, 44, 53, 62, 71. Only [8] works
* for Power key in Keypad driver, so we set KEY_ENDCALL in [8] because
* EndCall key is Power key in Android. If KPD_PWRKEY_USE_EINT is YES, these
* eight keycodes will not work for Power key.
*/
#define KPD_KEY_DEBOUNCE 1024 /* (val / 32) ms */
#define KPD_PWRKEY_MAP KEY_POWER
#define MTK_PMIC_PWR_KEY 8
/* HW keycode [0 ~ 71] -> Linux keycode */
#define KPD_INIT_KEYMAP() \
{ \
[0] = KEY_VOLUMEUP, \
[1] = KEY_VOLUMEDOWN, \
}
/*****************************************************************/
/*******************Preload Customation***************************/
/*****************************************************************/
#define KPD_PWRKEY_EINT_GPIO GPIO0
#define KPD_PWRKEY_GPIO_DIN 0
#define KPD_DL_KEY1 0 /* KEY_VOLUMEUP */
#define KPD_DL_KEY2 1 /* KEY_VOLUMEDOWN */
#define KPD_DL_KEY3 8 /* KEY_POWER */
/*****************************************************************/
/*******************Uboot Customation***************************/
/*****************************************************************/
#define MT65XX_RECOVERY_KEY 0 /* KEY_VOLUMEUP */
#define MT65XX_FACTORY_KEY 1 /* KEY_VOLUMEDOWN */
/*****************************************************************/
/*******************factory Customation***************************/
/*****************************************************************/
#define KEYS_PWRKEY_MAP { KEY_POWER, "Power" }
#define DEFINE_KEYS_KEYMAP(x) \
struct key x[] = { \
KEYS_PWRKEY_MAP, \
{ KEY_VOLUMEUP, "VLUp" }, \
{ KEY_VOLUMEDOWN, "VLDown" }, \
}
#define CUST_KEY_UP KEY_VOLUMEUP
#define CUST_KEY_VOLUP KEY_VOLUMEUP
#define CUST_KEY_DOWN KEY_VOLUMEDOWN
#define CUST_KEY_VOLDOWN KEY_VOLUMEDOWN
#define CUST_KEY_CONFIRM KEY_VOLUMEUP
/*****************************************************************/
/*******************recovery Customation****************************/
/*****************************************************************/
#endif
arch/arm/mach-mt8127/ford/dct/dct_austin/cust_power.h
Executable
+9
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@@ -0,0 +1,9 @@
/*
* Generated by MTK SP DrvGen Version 03.13.6 for MT8127. Copyright MediaTek Inc. (C) 2013.
* Thu Jan 29 20:42:51 2015
* Do Not Modify the File.
*/
#define GPIO_DVDD28_DPI GPIO_VIO28
arch/arm/mach-mt8127/ford/dct/dct_austin/pmic_drv.c
Executable
+16
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@@ -0,0 +1,16 @@
/*
* Generated by MTK SP Drv_CodeGen Version 03.13.6 for MT8127. Copyright MediaTek Inc. (C) 2013.
* Thu Jan 29 20:42:51 2015
* Do Not Modify the File.
*/
#include "pmic_drv.h"
//For PMIC driver use
arch/arm/mach-mt8127/ford/dct/dct_austin/pmic_drv.h
Executable
+30
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@@ -0,0 +1,30 @@
/*
* Generated by MTK SP Drv_CodeGen Version 03.13.6 for MT8127. Copyright MediaTek Inc. (C) 2013.
* Thu Jan 29 20:42:51 2015
* Do Not Modify the File.
*/
#include <mach/upmu_sw.h>
//****for customer use*******//
//PMIC default enable/disable result
//PMIC mode select
typedef enum
{
BY_ENABLE = 0,
BY_SRCLKEN = 1
}MODE_sel_enum;
////For Common use
//For PMIC driver use
drivers/misc/mediatek/imgsensor/src/mt8127/hi708_yuv/Makefile → arch/arm/mach-mt8127/ford/eeprom/Makefile
Regular → Executable
+1 -1
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@@ -1,4 +1,4 @@
include $(srctree)/drivers/misc/mediatek/Makefile.custom
obj-y += hi708yuv_Sensor.o
obj-y := dummy_eeprom.o
arch/arm/mach-mt8127/ford/eeprom/dummy_eeprom.c
+643
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@@ -0,0 +1,643 @@
/*
* Driver for EEPROM
*
*
*/
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/cdev.h>
#include <linux/uaccess.h>
#include <linux/slab.h>
#include <linux/fs.h>
#include "kd_camera_hw.h"
#include "eeprom.h"
#include "eeprom_define.h"
#include "dummy_eeprom.h"
#include <asm/system.h> // for SMP
//#define EEPROMGETDLT_DEBUG //test
//#define EEPROM_DEBUG //test
#ifdef EEPROM_DEBUG
#define EEPROMDB printk
#else
#define EEPROMDB(x,...)
#endif
static DEFINE_SPINLOCK(g_EEPROMLock); // for SMP
#define EEPROM_I2C_BUSNUM 1
static struct i2c_board_info __initdata kd_eeprom_dev={ I2C_BOARD_INFO("dummy_eeprom", 0xA0>>1)};
/*******************************************************************************
*
********************************************************************************/
#define EEPROM_ICS_REVISION 1 //seanlin111208
/*******************************************************************************
*
********************************************************************************/
#define EEPROM_DRVNAME "dummy_eeprom"
#define EEPROM_I2C_GROUP_ID 0
/*******************************************************************************
*
********************************************************************************/
/* fix warning MSG
static unsigned short g_pu2Normal_i2c[] = {S24CS64A_DEVICE_ID , I2C_CLIENT_END};
static unsigned short g_u2Ignore = I2C_CLIENT_END;
static struct i2c_client_address_data g_stEEPROM_Addr_data = {
.normal_i2c = g_pu2Normal_i2c,
.probe = &g_u2Ignore,
.ignore = &g_u2Ignore
}; */
static struct i2c_client * g_pstI2Cclient = NULL;
//81 is used for V4L driver
static dev_t g_EEPROMdevno = MKDEV(EEPROM_DEV_MAJOR_NUMBER,0);
static struct cdev * g_pEEPROM_CharDrv = NULL;
//static spinlock_t g_EEPROMLock;
static struct class *EEPROM_class = NULL;
static atomic_t g_EEPROMatomic;
/*******************************************************************************
*
********************************************************************************/
// maximun read length is limited at "I2C_FIFO_SIZE" in I2c-mt65xx.c which is 8 bytes
int iWriteEEPROM(u16 a_u2Addr , u32 a_u4Bytes, u8 * puDataInBytes)
{
int i4RetValue = 0;
u32 u4Index = 0;
char puSendCmd[8] = {(char)(a_u2Addr >> 8) , (char)(a_u2Addr & 0xFF) ,
0, 0, 0, 0, 0, 0};
if(a_u4Bytes + 2 > 8)
{
EEPROMDB("[EEPROM] exceed I2c-mt65xx.c 8 bytes limitation (include address 2 Byte)\n");
return -1;
}
for(u4Index = 0 ; u4Index < a_u4Bytes ; u4Index += 1 )
{
puSendCmd[(u4Index + 2)] = puDataInBytes[u4Index];
}
i4RetValue = i2c_master_send(g_pstI2Cclient, puSendCmd, (a_u4Bytes + 2));
if (i4RetValue != (a_u4Bytes + 2))
{
EEPROMDB("[EEPROM] I2C write failed!! \n");
return -1;
}
mdelay(10); //for tWR singnal --> write data form buffer to memory.
//EEPROMDB("[EEPROM] iWriteEEPROM done!! \n");
return 0;
}
// maximun read length is limited at "I2C_FIFO_SIZE" in I2c-mt65xx.c which is 8 bytes
int iReadEEPROM(u16 a_u2Addr, u32 ui4_length, u8 * a_puBuff)
{
int i4RetValue = 0;
char puReadCmd[2] = {(char)(a_u2Addr >> 8) , (char)(a_u2Addr & 0xFF)};
//EEPROMDB("[EEPROM] iReadEEPROM!! \n");
if(ui4_length > 8)
{
EEPROMDB("[EEPROM] exceed I2c-mt65xx.c 8 bytes limitation\n");
return -1;
}
spin_lock(&g_EEPROMLock); //for SMP
g_pstI2Cclient->addr = g_pstI2Cclient->addr & (I2C_MASK_FLAG | I2C_WR_FLAG);
spin_unlock(&g_EEPROMLock); // for SMP
//EEPROMDB("[EERPOM] i2c_master_send \n");
i4RetValue = i2c_master_send(g_pstI2Cclient, puReadCmd, 2);
if (i4RetValue != 2)
{
EEPROMDB("[EEPROM] I2C send read address failed!! \n");
return -1;
}
//EEPROMDB("[EERPOM] i2c_master_recv \n");
i4RetValue = i2c_master_recv(g_pstI2Cclient, (char *)a_puBuff, ui4_length);
if (i4RetValue != ui4_length)
{
EEPROMDB("[EEPROM] I2C read data failed!! \n");
return -1;
}
spin_lock(&g_EEPROMLock); //for SMP
g_pstI2Cclient->addr = g_pstI2Cclient->addr & I2C_MASK_FLAG;
spin_unlock(&g_EEPROMLock); // for SMP
//EEPROMDB("[EEPROM] iReadEEPROM done!! \n");
return 0;
}
static int iWriteData(unsigned int ui4_offset, unsigned int ui4_length, unsigned char * pinputdata)
{
int i4RetValue = 0;
int i4ResidueDataLength;
u32 u4IncOffset = 0;
u32 u4CurrentOffset;
u8 * pBuff;
EEPROMDB("[EEPROM] iWriteData\n" );
if (ui4_offset + ui4_length >= 0x2000)
{
EEPROMDB("[EEPROM] Write Error!! S-24CS64A not supprt address >= 0x2000!! \n" );
return -1;
}
i4ResidueDataLength = (int)ui4_length;
u4CurrentOffset = ui4_offset;
pBuff = pinputdata;
EEPROMDB("[EEPROM] iWriteData u4CurrentOffset is %d \n",u4CurrentOffset);
do
{
if(i4ResidueDataLength >= 6)
{
i4RetValue = iWriteEEPROM((u16)u4CurrentOffset, 6, pBuff);
if (i4RetValue != 0)
{
EEPROMDB("[EEPROM] I2C iWriteData failed!! \n");
return -1;
}
u4IncOffset += 6;
i4ResidueDataLength -= 6;
u4CurrentOffset = ui4_offset + u4IncOffset;
pBuff = pinputdata + u4IncOffset;
}
else
{
i4RetValue = iWriteEEPROM((u16)u4CurrentOffset, i4ResidueDataLength, pBuff);
if (i4RetValue != 0)
{
EEPROMDB("[EEPROM] I2C iWriteData failed!! \n");
return -1;
}
u4IncOffset += 6;
i4ResidueDataLength -= 6;
u4CurrentOffset = ui4_offset + u4IncOffset;
pBuff = pinputdata + u4IncOffset;
//break;
}
}while (i4ResidueDataLength > 0);
EEPROMDB("[EEPROM] iWriteData done\n" );
return 0;
}
//int iReadData(stEEPROM_INFO_STRUCT * st_pOutputBuffer)
static int iReadData(unsigned int ui4_offset, unsigned int ui4_length, unsigned char * pinputdata)
{
int i4RetValue = 0;
int i4ResidueDataLength;
u32 u4IncOffset = 0;
u32 u4CurrentOffset;
u8 * pBuff;
EEPROMDB("[EEPROM] iReadData \n" );
if (ui4_offset + ui4_length >= 0x2000)
{
EEPROMDB("[EEPROM] Read Error!! S-24CS64A not supprt address >= 0x2000!! \n" );
return -1;
}
i4ResidueDataLength = (int)ui4_length;
u4CurrentOffset = ui4_offset;
pBuff = pinputdata;
do
{
if(i4ResidueDataLength >= 8)
{
i4RetValue = iReadEEPROM((u16)u4CurrentOffset, 8, pBuff);
if (i4RetValue != 0)
{
EEPROMDB("[EEPROM] I2C iReadData failed!! \n");
return -1;
}
u4IncOffset += 8;
i4ResidueDataLength -= 8;
u4CurrentOffset = ui4_offset + u4IncOffset;
pBuff = pinputdata + u4IncOffset;
}
else
{
i4RetValue = iReadEEPROM((u16)u4CurrentOffset, i4ResidueDataLength, pBuff);
if (i4RetValue != 0)
{
EEPROMDB("[EEPROM] I2C iReadData failed!! \n");
return -1;
}
u4IncOffset += 8;
i4ResidueDataLength -= 8;
u4CurrentOffset = ui4_offset + u4IncOffset;
pBuff = pinputdata + u4IncOffset;
//break;
}
}while (i4ResidueDataLength > 0);
//fix warning MSG EEPROMDB("[EEPROM] iReadData finial address is %d length is %d buffer address is 0x%x\n",u4CurrentOffset, i4ResidueDataLength, pBuff);
EEPROMDB("[EEPROM] iReadData done\n" );
return 0;
}
/*******************************************************************************
*
********************************************************************************/
#define NEW_UNLOCK_IOCTL
#ifndef NEW_UNLOCK_IOCTL
static int EEPROM_Ioctl(struct inode * a_pstInode,
struct file * a_pstFile,
unsigned int a_u4Command,
unsigned long a_u4Param)
#else
static long EEPROM_Ioctl(
struct file *file,
unsigned int a_u4Command,
unsigned long a_u4Param
)
#endif
{
int i4RetValue = 0;
u8 * pBuff = NULL;
u8 * pWorkingBuff = NULL;
stEEPROM_INFO_STRUCT *ptempbuf;
#ifdef EEPROMGETDLT_DEBUG
struct timeval ktv1, ktv2;
unsigned long TimeIntervalUS;
#endif
if(_IOC_NONE == _IOC_DIR(a_u4Command))
{
}
else
{
pBuff = (u8 *)kmalloc(sizeof(stEEPROM_INFO_STRUCT),GFP_KERNEL);
if(NULL == pBuff)
{
EEPROMDB("[EEPROM] ioctl allocate mem failed\n");
return -ENOMEM;
}
if(_IOC_WRITE & _IOC_DIR(a_u4Command))
{
if(copy_from_user((u8 *) pBuff , (u8 *) a_u4Param, sizeof(stEEPROM_INFO_STRUCT)))
{ //get input structure address
kfree(pBuff);
EEPROMDB("[EEPROM] ioctl copy from user failed\n");
return -EFAULT;
}
}
}
ptempbuf = (stEEPROM_INFO_STRUCT *)pBuff;
pWorkingBuff = (u8*)kmalloc(ptempbuf->u4Length,GFP_KERNEL);
if(NULL == pWorkingBuff)
{
kfree(pBuff);
EEPROMDB("[EEPROM] ioctl allocate mem failed\n");
return -ENOMEM;
}
//fix warning MSG EEPROMDB("[EEPROM] init Working buffer address 0x%x command is 0x%08x\n", pWorkingBuff, a_u4Command);
if(copy_from_user((u8*)pWorkingBuff , (u8*)ptempbuf->pu1Params, ptempbuf->u4Length))
{
kfree(pBuff);
kfree(pWorkingBuff);
EEPROMDB("[EEPROM] ioctl copy from user failed\n");
return -EFAULT;
}
switch(a_u4Command)
{
case EEPROMIOC_S_WRITE:
EEPROMDB("[EEPROM] Write CMD \n");
#ifdef EEPROMGETDLT_DEBUG
do_gettimeofday(&ktv1);
#endif
i4RetValue = iWriteData((u16)ptempbuf->u4Offset, ptempbuf->u4Length, pWorkingBuff);
#ifdef EEPROMGETDLT_DEBUG
do_gettimeofday(&ktv2);
if(ktv2.tv_sec > ktv1.tv_sec)
{
TimeIntervalUS = ktv1.tv_usec + 1000000 - ktv2.tv_usec;
}
else
{
TimeIntervalUS = ktv2.tv_usec - ktv1.tv_usec;
}
printk("Write data %d bytes take %lu us\n",ptempbuf->u4Length, TimeIntervalUS);
#endif
break;
case EEPROMIOC_G_READ:
EEPROMDB("[EEPROM] Read CMD \n");
#ifdef EEPROMGETDLT_DEBUG
do_gettimeofday(&ktv1);
#endif
EEPROMDB("[EEPROM] offset %d \n", ptempbuf->u4Offset);
EEPROMDB("[EEPROM] length %d \n", ptempbuf->u4Length);
//fix warning MSG EEPROMDB("[EEPROM] Before read Working buffer address 0x%x \n", pWorkingBuff);
i4RetValue = iReadData((u16)ptempbuf->u4Offset, ptempbuf->u4Length, pWorkingBuff);
//fix warning MSG EEPROMDB("[EEPROM] After read Working buffer address 0x%x \n", pWorkingBuff);
#ifdef EEPROMGETDLT_DEBUG
do_gettimeofday(&ktv2);
if(ktv2.tv_sec > ktv1.tv_sec)
{
TimeIntervalUS = ktv1.tv_usec + 1000000 - ktv2.tv_usec;
}
else
{
TimeIntervalUS = ktv2.tv_usec - ktv1.tv_usec;
}
printk("Read data %d bytes take %lu us\n",ptempbuf->u4Length, TimeIntervalUS);
#endif
break;
default :
EEPROMDB("[EEPROM] No CMD \n");
i4RetValue = -EPERM;
break;
}
if(_IOC_READ & _IOC_DIR(a_u4Command))
{
//copy data to user space buffer, keep other input paremeter unchange.
EEPROMDB("[EEPROM] to user length %d \n", ptempbuf->u4Length);
//fix warning MSG EEPROMDB("[EEPROM] to user Working buffer address 0x%x \n", pWorkingBuff);
if(copy_to_user((u8 __user *) ptempbuf->pu1Params , (u8 *)pWorkingBuff , ptempbuf->u4Length))
{
kfree(pBuff);
kfree(pWorkingBuff);
EEPROMDB("[EEPROM] ioctl copy to user failed\n");
return -EFAULT;
}
}
kfree(pBuff);
kfree(pWorkingBuff);
return i4RetValue;
}
static u32 g_u4Opened = 0;
//#define
//Main jobs:
// 1.check for device-specified errors, device not ready.
// 2.Initialize the device if it is opened for the first time.
static int EEPROM_Open(struct inode * a_pstInode, struct file * a_pstFile)
{
EEPROMDB("[S24EEPROM] EEPROM_Open\n");
spin_lock(&g_EEPROMLock);
if(g_u4Opened)
{
spin_unlock(&g_EEPROMLock);
return -EBUSY;
}
else
{
g_u4Opened = 1;
atomic_set(&g_EEPROMatomic,0);
}
spin_unlock(&g_EEPROMLock);
//if(TRUE != hwPowerOn(MT65XX_POWER_LDO_VCAMA, VOL_2800, "S24CS64A"))
//{
// EEPROMDB("[EEPROM] Fail to enable analog gain\n");
// return -EIO;
//}
return 0;
}
//Main jobs:
// 1.Deallocate anything that "open" allocated in private_data.
// 2.Shut down the device on last close.
// 3.Only called once on last time.
// Q1 : Try release multiple times.
static int EEPROM_Release(struct inode * a_pstInode, struct file * a_pstFile)
{
spin_lock(&g_EEPROMLock);
g_u4Opened = 0;
atomic_set(&g_EEPROMatomic,0);
spin_unlock(&g_EEPROMLock);
return 0;
}
static const struct file_operations g_stEEPROM_fops =
{
.owner = THIS_MODULE,
.open = EEPROM_Open,
.release = EEPROM_Release,
//.ioctl = EEPROM_Ioctl
.unlocked_ioctl = EEPROM_Ioctl
};
#define EEPROM_DYNAMIC_ALLOCATE_DEVNO 1
inline static int RegisterEEPROMCharDrv(void)
{
struct device* EEPROM_device = NULL;
#if EEPROM_DYNAMIC_ALLOCATE_DEVNO
if( alloc_chrdev_region(&g_EEPROMdevno, 0, 1,EEPROM_DRVNAME) )
{
EEPROMDB("[EEPROM] Allocate device no failed\n");
return -EAGAIN;
}
#else
if( register_chrdev_region( g_EEPROMdevno , 1 , EEPROM_DRVNAME) )
{
EEPROMDB("[EEPROM] Register device no failed\n");
return -EAGAIN;
}
#endif
//Allocate driver
g_pEEPROM_CharDrv = cdev_alloc();
if(NULL == g_pEEPROM_CharDrv)
{
unregister_chrdev_region(g_EEPROMdevno, 1);
EEPROMDB("[EEPROM] Allocate mem for kobject failed\n");
return -ENOMEM;
}
//Attatch file operation.
cdev_init(g_pEEPROM_CharDrv, &g_stEEPROM_fops);
g_pEEPROM_CharDrv->owner = THIS_MODULE;
//Add to system
if(cdev_add(g_pEEPROM_CharDrv, g_EEPROMdevno, 1))
{
EEPROMDB("[EEPROM] Attatch file operation failed\n");
unregister_chrdev_region(g_EEPROMdevno, 1);
return -EAGAIN;
}
EEPROM_class = class_create(THIS_MODULE, "EEPROMdrv");
if (IS_ERR(EEPROM_class)) {
int ret = PTR_ERR(EEPROM_class);
EEPROMDB("Unable to create class, err = %d\n", ret);
return ret;
}
EEPROM_device = device_create(EEPROM_class, NULL, g_EEPROMdevno, NULL, EEPROM_DRVNAME);
return 0;
}
inline static void UnregisterEEPROMCharDrv(void)
{
//Release char driver
cdev_del(g_pEEPROM_CharDrv);
unregister_chrdev_region(g_EEPROMdevno, 1);
device_destroy(EEPROM_class, g_EEPROMdevno);
class_destroy(EEPROM_class);
}
//////////////////////////////////////////////////////////////////////
#ifndef EEPROM_ICS_REVISION
static int EEPROM_i2c_detect(struct i2c_client *client, int kind, struct i2c_board_info *info);
#elif 0
static int EEPROM_i2c_detect(struct i2c_client *client, struct i2c_board_info *info);
#else
#endif
static int EEPROM_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id);
static int EEPROM_i2c_remove(struct i2c_client *);
static const struct i2c_device_id EEPROM_i2c_id[] = {{EEPROM_DRVNAME,0},{}};
#if 0 //test110314 Please use the same I2C Group ID as Sensor
static unsigned short force[] = {EEPROM_I2C_GROUP_ID, S24CS64A_DEVICE_ID, I2C_CLIENT_END, I2C_CLIENT_END};
#else
//static unsigned short force[] = {EEPROM_I2C_GROUP_ID, S24CS64A_DEVICE_ID, I2C_CLIENT_END, I2C_CLIENT_END};
#endif
//static const unsigned short * const forces[] = { force, NULL };
//static struct i2c_client_address_data addr_data = { .forces = forces,};
static struct i2c_driver EEPROM_i2c_driver = {
.probe = EEPROM_i2c_probe,
.remove = EEPROM_i2c_remove,
// .detect = EEPROM_i2c_detect,
.driver.name = EEPROM_DRVNAME,
.id_table = EEPROM_i2c_id,
};
#ifndef EEPROM_ICS_REVISION
static int EEPROM_i2c_detect(struct i2c_client *client, int kind, struct i2c_board_info *info) {
strcpy(info->type, EEPROM_DRVNAME);
return 0;
}
#endif
static int EEPROM_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id) {
int i4RetValue = 0;
EEPROMDB("[EEPROM] Attach I2C \n");
// spin_lock_init(&g_EEPROMLock);
//get sensor i2c client
spin_lock(&g_EEPROMLock); //for SMP
g_pstI2Cclient = client;
g_pstI2Cclient->addr = S24CS64A_DEVICE_ID>>1;
spin_unlock(&g_EEPROMLock); // for SMP
EEPROMDB("[EEPROM] g_pstI2Cclient->addr = 0x%8x \n",g_pstI2Cclient->addr);
//Register char driver
i4RetValue = RegisterEEPROMCharDrv();
if(i4RetValue){
EEPROMDB("[EEPROM] register char device failed!\n");
return i4RetValue;
}
EEPROMDB("[EEPROM] Attached!! \n");
return 0;
}
static int EEPROM_i2c_remove(struct i2c_client *client)
{
return 0;
}
static int EEPROM_probe(struct platform_device *pdev)
{
return i2c_add_driver(&EEPROM_i2c_driver);
}
static int EEPROM_remove(struct platform_device *pdev)
{
i2c_del_driver(&EEPROM_i2c_driver);
return 0;
}
// platform structure
static struct platform_driver g_stEEPROM_Driver = {
.probe = EEPROM_probe,
.remove = EEPROM_remove,
.driver = {
.name = EEPROM_DRVNAME,
.owner = THIS_MODULE,
}
};
static struct platform_device g_stEEPROM_Device = {
.name = EEPROM_DRVNAME,
.id = 0,
.dev = {
}
};
static int __init EEPROM_i2C_init(void)
{
i2c_register_board_info(EEPROM_I2C_BUSNUM, &kd_eeprom_dev, 1);
if(platform_driver_register(&g_stEEPROM_Driver)){
EEPROMDB("failed to register EEPROM driver\n");
return -ENODEV;
}
if (platform_device_register(&g_stEEPROM_Device))
{
EEPROMDB("failed to register EEPROM driver\n");
return -ENODEV;
}
return 0;
}
static void __exit EEPROM_i2C_exit(void)
{
platform_driver_unregister(&g_stEEPROM_Driver);
}
module_init(EEPROM_i2C_init);
module_exit(EEPROM_i2C_exit);
MODULE_DESCRIPTION("EEPROM driver");
MODULE_AUTHOR("Sean Lin <Sean.Lin@Mediatek.com>");
MODULE_LICENSE("GPL");
arch/arm/mach-mt8127/ford/eeprom/dummy_eeprom.h
+30
View File
@@ -0,0 +1,30 @@
/*****************************************************************************
*
* Filename:
* ---------
* S-24CS64A.h
*
* Project:
* --------
* ALPS
*
* Description:
* ------------
* Header file of EEPROM driver
*
*
* Author:
* -------
* Ronnie Lai (MTK01420)
*
*============================================================================*/
#ifndef __EEPROM_H
#define __EEPROM_H
#define EEPROM_DEV_MAJOR_NUMBER 226
/* EEPROM READ/WRITE ID */
#define S24CS64A_DEVICE_ID 0xA0 //0xFE //
#endif /* __EEPROM_H */
arch/arm/mach-mt8127/ford/eeprom/inc/eeprom.h
+27
View File
@@ -0,0 +1,27 @@
#ifndef _EEPROM_H
#define _EEPROM_H
#include <linux/ioctl.h>
#define EEPROMAGIC 'i'
//IOCTRL(inode * ,file * ,cmd ,arg )
//S means "set through a ptr"
//T means "tell by a arg value"
//G means "get by a ptr"
//Q means "get by return a value"
//X means "switch G and S atomically"
//H means "switch T and Q atomically"
/*******************************************************************************
*
********************************************************************************/
//EEPROM write
#define EEPROMIOC_S_WRITE _IOW(EEPROMAGIC,0,stEEPROM_INFO_STRUCT)
//EEPROM read
#define EEPROMIOC_G_READ _IOWR(EEPROMAGIC,5,stPEEPROM_INFO_STRUCT)
#endif //_EEPROM_H
arch/arm/mach-mt8127/ford/eeprom/inc/eeprom_define.h
+12
View File
@@ -0,0 +1,12 @@
#ifndef _EEPROM_DATA_H
#define _EEPROM_DATA_H
//#define MT6516ISP_MaxTableSize_CNT 4096
//#define EEPROM_DBG_MESSAGE
typedef struct{
u32 u4Offset;
u32 u4Length;
u8 * pu1Params;
}stEEPROM_INFO_STRUCT, *stPEEPROM_INFO_STRUCT;
#endif //_EEPROM_DATA_H
arch/arm/mach-mt8127/ford/flashlight/constant_flashlight/Makefile
Executable
+3
View File
@@ -0,0 +1,3 @@
include $(srctree)/drivers/misc/mediatek/Makefile.custom
obj-y += leds_strobe.o
arch/arm/mach-mt8127/ford/flashlight/constant_flashlight/leds_strobe.c
+401
View File
@@ -0,0 +1,401 @@
#include <linux/kernel.h> //constant xx
#include <linux/module.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/wait.h>
#include <linux/slab.h>
#include <linux/fs.h>
#include <linux/sched.h>
#include <linux/poll.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/cdev.h>
#include <linux/errno.h>
#include <linux/time.h>
#include "kd_flashlight.h"
#include <asm/io.h>
#include <asm/uaccess.h>
#include "kd_camera_hw.h"
#include <cust_gpio_usage.h>
#include <linux/hrtimer.h>
#include <linux/ktime.h>
#include <linux/xlog.h>
#include <linux/version.h>
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
#include <linux/mutex.h>
#else
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
#include <linux/semaphore.h>
#else
#include <asm/semaphore.h>
#endif
#endif
/******************************************************************************
* Debug configuration
******************************************************************************/
// availible parameter
// ANDROID_LOG_ASSERT
// ANDROID_LOG_ERROR
// ANDROID_LOG_WARNING
// ANDROID_LOG_INFO
// ANDROID_LOG_DEBUG
// ANDROID_LOG_VERBOSE
#define TAG_NAME "leds_strobe.c"
#define PK_DBG_NONE(fmt, arg...) do {} while (0)
#define PK_DBG_FUNC(fmt, arg...) xlog_printk(ANDROID_LOG_DEBUG , TAG_NAME, KERN_INFO "%s: " fmt, __FUNCTION__ ,##arg)
#define PK_WARN(fmt, arg...) xlog_printk(ANDROID_LOG_WARNING, TAG_NAME, KERN_WARNING "%s: " fmt, __FUNCTION__ ,##arg)
#define PK_NOTICE(fmt, arg...) xlog_printk(ANDROID_LOG_DEBUG , TAG_NAME, KERN_NOTICE "%s: " fmt, __FUNCTION__ ,##arg)
#define PK_INFO(fmt, arg...) xlog_printk(ANDROID_LOG_INFO , TAG_NAME, KERN_INFO "%s: " fmt, __FUNCTION__ ,##arg)
#define PK_TRC_FUNC(f) xlog_printk(ANDROID_LOG_DEBUG , TAG_NAME, "<%s>\n", __FUNCTION__);
#define PK_TRC_VERBOSE(fmt, arg...) xlog_printk(ANDROID_LOG_VERBOSE, TAG_NAME, fmt, ##arg)
#define PK_ERROR(fmt, arg...) xlog_printk(ANDROID_LOG_ERROR , TAG_NAME, KERN_ERR "%s: " fmt, __FUNCTION__ ,##arg)
#define DEBUG_LEDS_STROBE
#ifdef DEBUG_LEDS_STROBE
#define PK_DBG PK_DBG_FUNC
#define PK_VER PK_TRC_VERBOSE
#define PK_ERR PK_ERROR
#else
#define PK_DBG(a,...)
#define PK_VER(a,...)
#define PK_ERR(a,...)
#endif
/******************************************************************************
* local variables
******************************************************************************/
static DEFINE_SPINLOCK(g_strobeSMPLock); /* cotta-- SMP proection */
static u32 strobe_Res = 0;
static u32 strobe_Timeus = 0;
static BOOL g_strobe_On = 0;
static int g_duty=-1;
static int g_timeOutTimeMs=0;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
static DEFINE_MUTEX(g_strobeSem);
#else
static DECLARE_MUTEX(g_strobeSem);
#endif
#define STROBE_DEVICE_ID 0x60
static struct work_struct workTimeOut;
/*****************************************************************************
Functions
*****************************************************************************/
#ifdef GPIO_CAMERA_FLASH_EN_PIN
#define GPIO_ENF GPIO_CAMERA_FLASH_EN_PIN
#else
#define GPIO_ENF 0xFF
#endif
#ifdef GPIO_CAMERA_FLASH_MODE_PIN
#define GPIO_ENT GPIO_CAMERA_FLASH_MODE_PIN
#define GPIO_ENT_IS_AVALIABLE 1
#else
#define GPIO_ENT 0xFF
#define GPIO_ENT_IS_AVALIABLE 0
#endif
/*CAMERA-FLASH-EN */
extern int iWriteRegI2C(u8 *a_pSendData , u16 a_sizeSendData, u16 i2cId);
extern int iReadRegI2C(u8 *a_pSendData , u16 a_sizeSendData, u8 * a_pRecvData, u16 a_sizeRecvData, u16 i2cId);
static void work_timeOutFunc(struct work_struct *data);
int FL_Enable(void)
{
if (g_duty==0)
{
#if 0
mt_set_gpio_out(GPIO_ENT,GPIO_OUT_ONE);
mt_set_gpio_out(GPIO_ENF,GPIO_OUT_ZERO);
#else
#if GPIO_ENT_IS_AVALIABLE
mt_set_gpio_out(GPIO_ENT,GPIO_OUT_ZERO);
#endif
mt_set_gpio_out(GPIO_ENF,GPIO_OUT_ONE);
#endif
PK_DBG(" FL_Enable line=%d\n",__LINE__);
}
else
{
#if GPIO_ENT_IS_AVALIABLE
mt_set_gpio_out(GPIO_ENT,GPIO_OUT_ZERO);
#endif
mt_set_gpio_out(GPIO_ENF,GPIO_OUT_ONE);
PK_DBG(" FL_Enable line=%d\n",__LINE__);
}
return 0;
}
int FL_Disable(void)
{
#if GPIO_ENT_IS_AVALIABLE
mt_set_gpio_out(GPIO_ENT,GPIO_OUT_ZERO);
#endif
mt_set_gpio_out(GPIO_ENF,GPIO_OUT_ZERO);
PK_DBG(" FL_Disable line=%d\n",__LINE__);
return 0;
}
int FL_dim_duty(kal_uint32 duty)
{
g_duty=duty;
PK_DBG(" FL_dim_duty line=%d\n",__LINE__);
return 0;
}
int FL_Init(void)
{
PK_DBG(" FL_Init - start line=%d\n",__LINE__);
PK_DBG(" GPIO_ENF=0x%x, GPIO_MODE_00=0x%x \n",GPIO_ENF,GPIO_MODE_00);
if (mt_set_gpio_mode(GPIO_ENF,GPIO_MODE_00))
{
PK_DBG("[constant_flashlight] set gpio mode failed!! \n");
}
if (mt_set_gpio_dir(GPIO_ENF,GPIO_DIR_OUT))
{
PK_DBG("[constant_flashlight] set gpio dir failed!! \n");
}
if (mt_set_gpio_out(GPIO_ENF,GPIO_OUT_ZERO))
{
PK_DBG("[constant_flashlight] set gpio failed!! \n");
}
/*Init. to disable*/
#if GPIO_ENT_IS_AVALIABLE
PK_DBG(" FL_Init - start line=%d\n",__LINE__);
if (mt_set_gpio_mode(GPIO_ENT,GPIO_MODE_00))
{
PK_DBG("[constant_flashlight] set gpio mode failed!! \n");
}
if (mt_set_gpio_dir(GPIO_ENT,GPIO_DIR_OUT))
{
PK_DBG("[constant_flashlight] set gpio dir failed!! \n");
}
if (mt_set_gpio_out(GPIO_ENT,GPIO_OUT_ZERO))
{
PK_DBG("[constant_flashlight] set gpio failed!! \n");
}
#endif
INIT_WORK(&workTimeOut, work_timeOutFunc);
PK_DBG(" FL_Init - end line=%d\n",__LINE__);
return 0;
}
int FL_Uninit(void)
{
FL_Disable();
return 0;
}
/*****************************************************************************
User interface
*****************************************************************************/
static void work_timeOutFunc(struct work_struct *data)
{
FL_Disable();
PK_DBG("ledTimeOut_callback\n");
//printk(KERN_ALERT "work handler function./n");
}
enum hrtimer_restart ledTimeOutCallback(struct hrtimer *timer)
{
schedule_work(&workTimeOut);
return HRTIMER_NORESTART;
}
static struct hrtimer g_timeOutTimer;
void timerInit(void)
{
g_timeOutTimeMs=1000; //1s
hrtimer_init( &g_timeOutTimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL );
g_timeOutTimer.function=ledTimeOutCallback;
}
static int constant_flashlight_ioctl(MUINT32 cmd, MUINT32 arg)
{
int i4RetValue = 0;
int ior_shift;
int iow_shift;
int iowr_shift;
ior_shift = cmd - (_IOR(FLASHLIGHT_MAGIC,0, int));
iow_shift = cmd - (_IOW(FLASHLIGHT_MAGIC,0, int));
iowr_shift = cmd - (_IOWR(FLASHLIGHT_MAGIC,0, int));
PK_DBG("constant_flashlight_ioctl() line=%d ior_shift=%d, iow_shift=%d iowr_shift=%d arg=%d\n",__LINE__, ior_shift, iow_shift, iowr_shift, arg);
switch (cmd)
{
case FLASH_IOC_SET_TIME_OUT_TIME_MS:
PK_DBG("FLASH_IOC_SET_TIME_OUT_TIME_MS: %d\n",arg);
g_timeOutTimeMs=arg;
break;
case FLASH_IOC_SET_DUTY :
PK_DBG("FLASHLIGHT_DUTY: %d\n",arg);
FL_dim_duty(arg);
break;
case FLASH_IOC_SET_STEP:
PK_DBG("FLASH_IOC_SET_STEP: %d\n",arg);
break;
case FLASH_IOC_SET_ONOFF :
PK_DBG("FLASHLIGHT_ONOFF: %d\n",arg);
if (arg==1)
{
if (g_timeOutTimeMs!=0)
{
ktime_t ktime;
ktime = ktime_set( 0, g_timeOutTimeMs*1000000 );
hrtimer_start( &g_timeOutTimer, ktime, HRTIMER_MODE_REL );
}
FL_Enable();
}
else
{
FL_Disable();
hrtimer_cancel( &g_timeOutTimer );
}
break;
default :
PK_DBG(" No such command \n");
i4RetValue = -EPERM;
break;
}
return i4RetValue;
}
static int constant_flashlight_open(void *pArg)
{
int i4RetValue = 0;
PK_DBG("constant_flashlight_open line=%d\n", __LINE__);
if (0 == strobe_Res)
{
FL_Init();
timerInit();
}
PK_DBG("constant_flashlight_open line=%d\n", __LINE__);
spin_lock_irq(&g_strobeSMPLock);
if (strobe_Res)
{
PK_ERR(" busy!\n");
i4RetValue = -EBUSY;
}
else
{
strobe_Res += 1;
}
spin_unlock_irq(&g_strobeSMPLock);
PK_DBG("constant_flashlight_open line=%d\n", __LINE__);
return i4RetValue;
}
static int constant_flashlight_release(void *pArg)
{
PK_DBG(" constant_flashlight_release\n");
if (strobe_Res)
{
spin_lock_irq(&g_strobeSMPLock);
strobe_Res = 0;
strobe_Timeus = 0;
/* LED On Status */
g_strobe_On = FALSE;
spin_unlock_irq(&g_strobeSMPLock);
FL_Uninit();
}
PK_DBG(" Done\n");
return 0;
}
FLASHLIGHT_FUNCTION_STRUCT constantFlashlightFunc=
{
constant_flashlight_open,
constant_flashlight_release,
constant_flashlight_ioctl
};
MUINT32 constantFlashlightInit(PFLASHLIGHT_FUNCTION_STRUCT *pfFunc)
{
if (pfFunc != NULL)
{
*pfFunc = &constantFlashlightFunc;
}
return 0;
}
/* LED flash control for high current capture mode*/
ssize_t strobe_VDIrq(void)
{
return 0;
}
EXPORT_SYMBOL(strobe_VDIrq);
arch/arm/mach-mt8127/ford/gyroscope/Makefile
Executable
+4
View File
@@ -0,0 +1,4 @@
include $(srctree)/drivers/misc/mediatek/Makefile.custom
obj-y := cust_gyro.o
arch/arm/mach-mt8127/ford/gyroscope/cust_gyro.c
+31
View File
@@ -0,0 +1,31 @@
#include <linux/types.h>
#include <mach/mt_pm_ldo.h>
#include <cust_gyro.h>
/*---------------------------------------------------------------------------*/
/*
int cust_gyro_power(struct gyro_hw *hw, unsigned int on, char* devname)
{
if (hw->power_id == MT65XX_POWER_NONE)
return 0;
if (on)
return hwPowerOn(hw->power_id, hw->power_vol, devname);
else
return hwPowerDown(hw->power_id, devname);
}
*/
/*---------------------------------------------------------------------------*/
static struct gyro_hw cust_gyro_hw = {
.addr = 0xd0,
.i2c_num = 2,
.direction = 7,
.power_id = MT65XX_POWER_NONE, /*!< LDO is not used */
.power_vol= VOL_DEFAULT, /*!< LDO is not used */
.firlen = 16, /*!< don't enable low pass fileter */
// .power = cust_gyro_power,
};
/*---------------------------------------------------------------------------*/
struct gyro_hw* get_cust_gyro_hw(void)
{
return &cust_gyro_hw;
}
arch/arm/mach-mt8127/ford/gyroscope/gyroscope.c
+799
View File
@@ -0,0 +1,799 @@
#include "gyroscope.h"
static struct gyro_context *gyro_context_obj = NULL;
static struct gyro_init_info* gyroscope_init_list[MAX_CHOOSE_GYRO_NUM]= {0}; //modified
static void gyro_early_suspend(struct early_suspend *h);
static void gyro_late_resume(struct early_suspend *h);
static void gyro_work_func(struct work_struct *work)
{
struct gyro_context *cxt = NULL;
int out_size;
//hwm_sensor_data sensor_data;
int x,y,z,status,div;
int64_t nt;
struct timespec time;
int err, idx;
cxt = gyro_context_obj;
if(NULL == cxt->gyro_data.get_data)
{
GYRO_ERR("gyro driver not register data path\n");
}
time.tv_sec = time.tv_nsec = 0;
time = get_monotonic_coarse();
nt = time.tv_sec*1000000000LL+time.tv_nsec;
//add wake lock to make sure data can be read before system suspend
cxt->gyro_data.get_data(&x,&y,&z,&status);
if(err)
{
GYRO_ERR("get gyro data fails!!\n" );
goto gyro_loop;
}
else
{
if((x != cxt->drv_data.gyro_data.values[0])
|| (y != cxt->drv_data.gyro_data.values[1])
|| (z != cxt->drv_data.gyro_data.values[2]))
{
if( 0 == x && 0==y
&& 0 == z)
{
goto gyro_loop;
}
cxt->drv_data.gyro_data.values[0] = x;
cxt->drv_data.gyro_data.values[1] = y;
cxt->drv_data.gyro_data.values[2] = z;
cxt->drv_data.gyro_data.status = status;
cxt->drv_data.gyro_data.time = nt;
}
}
if(true == cxt->is_first_data_after_enable)
{
cxt->is_first_data_after_enable = false;
//filter -1 value
if(GYRO_INVALID_VALUE == cxt->drv_data.gyro_data.values[0] ||
GYRO_INVALID_VALUE == cxt->drv_data.gyro_data.values[1] ||
GYRO_INVALID_VALUE == cxt->drv_data.gyro_data.values[2])
{
GYRO_LOG(" read invalid data \n");
goto gyro_loop;
}
}
//report data to input device
//printk("new gyro work run....\n");
//GYRO_LOG("gyro data[%d,%d,%d] \n" ,cxt->drv_data.gyro_data.values[0],
//cxt->drv_data.gyro_data.values[1],cxt->drv_data.gyro_data.values[2]);
gyro_data_report(cxt->drv_data.gyro_data.values[0],
cxt->drv_data.gyro_data.values[1],cxt->drv_data.gyro_data.values[2],
cxt->drv_data.gyro_data.status);
gyro_loop:
if(true == cxt->is_polling_run)
{
{
mod_timer(&cxt->timer, jiffies + atomic_read(&cxt->delay)/(1000/HZ));
}
}
}
static void gyro_poll(unsigned long data)
{
struct gyro_context *obj = (struct gyro_context *)data;
if(obj != NULL)
{
schedule_work(&obj->report);
}
}
static struct gyro_context *gyro_context_alloc_object(void)
{
struct gyro_context *obj = kzalloc(sizeof(*obj), GFP_KERNEL);
GYRO_LOG("gyro_context_alloc_object++++\n");
if(!obj)
{
GYRO_ERR("Alloc gyro object error!\n");
return NULL;
}
atomic_set(&obj->delay, 200); /*5Hz*/// set work queue delay time 200ms
atomic_set(&obj->wake, 0);
INIT_WORK(&obj->report, gyro_work_func);
init_timer(&obj->timer);
obj->timer.expires = jiffies + atomic_read(&obj->delay)/(1000/HZ);
obj->timer.function = gyro_poll;
obj->timer.data = (unsigned long)obj;
obj->is_first_data_after_enable = false;
obj->is_polling_run = false;
obj->is_batch_enable = false;
mutex_init(&obj->gyro_op_mutex);
GYRO_LOG("gyro_context_alloc_object----\n");
return obj;
}
static int gyro_real_enable(int enable)
{
int err =0;
struct gyro_context *cxt = NULL;
cxt = gyro_context_obj;
if(1==enable)
{
if(true==cxt->is_active_data || true ==cxt->is_active_nodata)
{
err = cxt->gyro_ctl.enable_nodata(1);
if(err)
{
err = cxt->gyro_ctl.enable_nodata(1);
if(err)
{
err = cxt->gyro_ctl.enable_nodata(1);
if(err)
GYRO_ERR("gyro enable(%d) err 3 timers = %d\n", enable, err);
}
}
GYRO_LOG("gyro real enable \n" );
}
}
if(0==enable)
{
if(false==cxt->is_active_data && false ==cxt->is_active_nodata)
{
err = cxt->gyro_ctl.enable_nodata(0);
if(err)
{
GYRO_ERR("gyro enable(%d) err = %d\n", enable, err);
}
GYRO_LOG("gyro real disable \n" );
}
}
return err;
}
static int gyro_enable_data(int enable)
{
struct gyro_context *cxt = NULL;
int err =0;
cxt = gyro_context_obj;
if(NULL == cxt->gyro_ctl.open_report_data)
{
GYRO_ERR("no gyro control path\n");
return -1;
}
if(1 == enable)
{
GYRO_LOG("gyro enable data\n");
cxt->is_active_data =true;
cxt->is_first_data_after_enable = true;
cxt->gyro_ctl.open_report_data(1);
if(false == cxt->is_polling_run && cxt->is_batch_enable == false)
{
if(false == cxt->gyro_ctl.is_report_input_direct)
{
mod_timer(&cxt->timer, jiffies + atomic_read(&cxt->delay)/(1000/HZ));
cxt->is_polling_run = true;
}
}
}
if(0 == enable)
{
GYRO_LOG("gyro disable \n");
cxt->is_active_data =false;
cxt->gyro_ctl.open_report_data(0);
if(true == cxt->is_polling_run)
{
if(false == cxt->gyro_ctl.is_report_input_direct)
{
cxt->is_polling_run = false;
del_timer_sync(&cxt->timer);
cancel_work_sync(&cxt->report);
cxt->drv_data.gyro_data.values[0] = GYRO_INVALID_VALUE;
cxt->drv_data.gyro_data.values[1] = GYRO_INVALID_VALUE;
cxt->drv_data.gyro_data.values[2] = GYRO_INVALID_VALUE;
}
}
}
gyro_real_enable(enable);
return 0;
}
int gyro_enable_nodata(int enable)
{
struct gyro_context *cxt = NULL;
int err =0;
cxt = gyro_context_obj;
if(NULL == cxt->gyro_ctl.enable_nodata)
{
GYRO_ERR("gyro_enable_nodata:gyro ctl path is NULL\n");
return -1;
}
if(1 == enable)
{
cxt->is_active_nodata = true;
}
if(0 == enable)
{
cxt->is_active_nodata = false;
}
gyro_real_enable(enable);
return 0;
}
static ssize_t gyro_show_enable_nodata(struct device* dev,
struct device_attribute *attr, char *buf)
{
int len = 0;
GYRO_LOG(" not support now\n");
return len;
}
static ssize_t gyro_store_enable_nodata(struct device* dev, struct device_attribute *attr,
const char *buf, size_t count)
{
GYRO_LOG("gyro_store_enable nodata buf=%s\n",buf);
mutex_lock(&gyro_context_obj->gyro_op_mutex);
struct gyro_context *cxt = NULL;
int err =0;
cxt = gyro_context_obj;
if(NULL == cxt->gyro_ctl.enable_nodata)
{
GYRO_LOG("gyro_ctl enable nodata NULL\n");
mutex_unlock(&gyro_context_obj->gyro_op_mutex);
return count;
}
if (!strncmp(buf, "1", 1))
{
gyro_enable_nodata(1);
}
else if (!strncmp(buf, "0", 1))
{
gyro_enable_nodata(0);
}
else
{
GYRO_ERR(" gyro_store enable nodata cmd error !!\n");
}
mutex_unlock(&gyro_context_obj->gyro_op_mutex);
}
static ssize_t gyro_store_active(struct device* dev, struct device_attribute *attr,
const char *buf, size_t count)
{
GYRO_LOG("gyro_store_active buf=%s\n",buf);
mutex_lock(&gyro_context_obj->gyro_op_mutex);
struct gyro_context *cxt = NULL;
int err =0;
cxt = gyro_context_obj;
if(NULL == cxt->gyro_ctl.open_report_data)
{
GYRO_LOG("gyro_ctl enable NULL\n");
mutex_unlock(&gyro_context_obj->gyro_op_mutex);
return count;
}
if (!strncmp(buf, "1", 1))
{
// cxt->gyro_ctl.enable(1);
gyro_enable_data(1);
}
else if (!strncmp(buf, "0", 1))
{
//cxt->gyro_ctl.enable(0);
gyro_enable_data(0);
}
else
{
GYRO_ERR(" gyro_store_active error !!\n");
}
mutex_unlock(&gyro_context_obj->gyro_op_mutex);
GYRO_LOG(" gyro_store_active done\n");
return count;
}
/*----------------------------------------------------------------------------*/
static ssize_t gyro_show_active(struct device* dev,
struct device_attribute *attr, char *buf)
{
struct gyro_context *cxt = NULL;
cxt = gyro_context_obj;
int len = 0;
GYRO_LOG("gyro show active not support now\n");
int div=cxt->gyro_data.vender_div;
GYRO_LOG("gyro vender_div value: %d\n", div);
return snprintf(buf, PAGE_SIZE, "%d\n", div);
//return len;
}
static ssize_t gyro_store_delay(struct device* dev, struct device_attribute *attr,
const char *buf, size_t count)
{
mutex_lock(&gyro_context_obj->gyro_op_mutex);
struct gyro_context *devobj = (struct gyro_context*)dev_get_drvdata(dev);
int delay;
int mdelay=0;
struct gyro_context *cxt = NULL;
int err =0;
cxt = gyro_context_obj;
if(NULL == cxt->gyro_ctl.set_delay)
{
GYRO_LOG("gyro_ctl set_delay NULL\n");
mutex_unlock(&gyro_context_obj->gyro_op_mutex);
return count;
}
if (1 != sscanf(buf, "%d", &delay)) {
GYRO_ERR("invalid format!!\n");
mutex_unlock(&gyro_context_obj->gyro_op_mutex);
return count;
}
if(false == cxt->gyro_ctl.is_report_input_direct)
{
mdelay = (int)delay/1000/1000;
atomic_set(&gyro_context_obj->delay, mdelay);
}
cxt->gyro_ctl.set_delay(delay);
GYRO_LOG(" gyro_delay %d ns\n",delay);
mutex_unlock(&gyro_context_obj->gyro_op_mutex);
return count;
}
static ssize_t gyro_show_delay(struct device* dev,
struct device_attribute *attr, char *buf)
{
int len = 0;
GYRO_LOG(" not support now\n");
return len;
}
static ssize_t gyro_store_batch(struct device* dev, struct device_attribute *attr,
const char *buf, size_t count)
{
GYRO_LOG("gyro_store_batch buf=%s\n",buf);
mutex_lock(&gyro_context_obj->gyro_op_mutex);
struct gyro_context *cxt = NULL;
int err =0;
cxt = gyro_context_obj;
if(cxt->gyro_ctl.is_support_batch){
if (!strncmp(buf, "1", 1))
{
cxt->is_batch_enable = true;
}
else if (!strncmp(buf, "0", 1))
{
cxt->is_batch_enable = false;
}
else
{
GYRO_ERR(" gyro_store_batch error !!\n");
}
}else{
GYRO_LOG(" gyro_store_batch not support\n");
}
mutex_unlock(&gyro_context_obj->gyro_op_mutex);
GYRO_LOG(" gyro_store_batch done: %d\n", cxt->is_batch_enable);
return count;
}
static ssize_t gyro_show_batch(struct device* dev,
struct device_attribute *attr, char *buf)
{
return snprintf(buf, PAGE_SIZE, "%d\n", 0);
}
static ssize_t gyro_store_flush(struct device* dev, struct device_attribute *attr,
const char *buf, size_t count)
{
mutex_lock(&gyro_context_obj->gyro_op_mutex);
struct gyro_context *devobj = (struct gyro_context*)dev_get_drvdata(dev);
//do read FIFO data function and report data immediately
mutex_unlock(&gyro_context_obj->gyro_op_mutex);
return count;
}
static ssize_t gyro_show_flush(struct device* dev,
struct device_attribute *attr, char *buf)
{
return snprintf(buf, PAGE_SIZE, "%d\n", 0);
}
static ssize_t gyro_show_devnum(struct device* dev,
struct device_attribute *attr, char *buf)
{
char *devname = NULL;
devname = dev_name(&gyro_context_obj->idev->dev);
return snprintf(buf, PAGE_SIZE, "%s\n", devname+5);
}
static int gyroscope_remove(struct platform_device *pdev)
{
GYRO_LOG("gyroscope_remove\n");
return 0;
}
static int gyroscope_probe(struct platform_device *pdev)
{
GYRO_LOG("gyroscope_probe\n");
return 0;
}
static struct platform_driver gyroscope_driver = {
.probe = gyroscope_probe,
.remove = gyroscope_remove,
.driver =
{
.name = "gyroscope",
}
};
static int gyro_real_driver_init(void)
{
int i =0;
int err=0;
GYRO_LOG(" gyro_real_driver_init +\n");
for(i = 0; i < MAX_CHOOSE_GYRO_NUM; i++)
{
GYRO_LOG(" i=%d\n",i);
if(0 != gyroscope_init_list[i])
{
GYRO_LOG(" gyro try to init driver %s\n", gyroscope_init_list[i]->name);
err = gyroscope_init_list[i]->init();
if(0 == err)
{
GYRO_LOG(" gyro real driver %s probe ok\n", gyroscope_init_list[i]->name);
break;
}
}
}
if(i == MAX_CHOOSE_GYRO_NUM)
{
GYRO_LOG(" gyro_real_driver_init fail\n");
err=-1;
}
return err;
}
int gyro_driver_add(struct gyro_init_info* obj)
{
int err=0;
int i =0;
GYRO_FUN(f);
for(i =0; i < MAX_CHOOSE_GYRO_NUM; i++ )
{
if(i == 0){
GYRO_LOG("register gyro driver for the first time\n");
if(platform_driver_register(&gyroscope_driver))
{
GYRO_ERR("failed to register gyro driver already exist\n");
}
}
if(NULL == gyroscope_init_list[i])
{
obj->platform_diver_addr = &gyroscope_driver;
gyroscope_init_list[i] = obj;
break;
}
}
if(NULL==gyroscope_init_list[i])
{
GYRO_ERR("gyro driver add err \n");
err=-1;
}
return err;
}
EXPORT_SYMBOL_GPL(gyro_driver_add);
static int gyro_misc_init(struct gyro_context *cxt)
{
int err=0;
cxt->mdev.minor = MISC_DYNAMIC_MINOR;
cxt->mdev.name = GYRO_MISC_DEV_NAME;
if((err = misc_register(&cxt->mdev)))
{
GYRO_ERR("unable to register gyro misc device!!\n");
}
return err;
}
static void gyro_input_destroy(struct gyro_context *cxt)
{
struct input_dev *dev = cxt->idev;
input_unregister_device(dev);
input_free_device(dev);
}
static int gyro_input_init(struct gyro_context *cxt)
{
struct input_dev *dev;
int err = 0;
dev = input_allocate_device();
if (NULL == dev)
return -ENOMEM;
dev->name = GYRO_INPUTDEV_NAME;
input_set_capability(dev, EV_ABS, EVENT_TYPE_GYRO_X);
input_set_capability(dev, EV_ABS, EVENT_TYPE_GYRO_Y);
input_set_capability(dev, EV_ABS, EVENT_TYPE_GYRO_Z);
input_set_capability(dev, EV_ABS, EVENT_TYPE_GYRO_STATUS);
input_set_abs_params(dev, EVENT_TYPE_GYRO_X, GYRO_VALUE_MIN, GYRO_VALUE_MAX, 0, 0);
input_set_abs_params(dev, EVENT_TYPE_GYRO_Y, GYRO_VALUE_MIN, GYRO_VALUE_MAX, 0, 0);
input_set_abs_params(dev, EVENT_TYPE_GYRO_Z, GYRO_VALUE_MIN, GYRO_VALUE_MAX, 0, 0);
input_set_abs_params(dev, EVENT_TYPE_GYRO_STATUS, GYRO_STATUS_MIN, GYRO_STATUS_MAX, 0, 0);
input_set_drvdata(dev, cxt);
err = input_register_device(dev);
if (err < 0) {
input_free_device(dev);
return err;
}
cxt->idev= dev;
return 0;
}
DEVICE_ATTR(gyroenablenodata, S_IWUSR | S_IRUGO, gyro_show_enable_nodata, gyro_store_enable_nodata);
DEVICE_ATTR(gyroactive, S_IWUSR | S_IRUGO, gyro_show_active, gyro_store_active);
DEVICE_ATTR(gyrodelay, S_IWUSR | S_IRUGO, gyro_show_delay, gyro_store_delay);
DEVICE_ATTR(gyrobatch, S_IWUSR | S_IRUGO, gyro_show_batch, gyro_store_batch);
DEVICE_ATTR(gyroflush, S_IWUSR | S_IRUGO, gyro_show_flush, gyro_store_flush);
DEVICE_ATTR(gyrodevnum, S_IWUSR | S_IRUGO, gyro_show_devnum, NULL);
static struct attribute *gyro_attributes[] = {
&dev_attr_gyroenablenodata.attr,
&dev_attr_gyroactive.attr,
&dev_attr_gyrodelay.attr,
&dev_attr_gyrobatch.attr,
&dev_attr_gyroflush.attr,
&dev_attr_gyrodevnum.attr,
NULL
};
static struct attribute_group gyro_attribute_group = {
.attrs = gyro_attributes
};
int gyro_register_data_path(struct gyro_data_path *data)
{
struct gyro_context *cxt = NULL;
int err =0;
cxt = gyro_context_obj;
cxt->gyro_data.get_data = data->get_data;
cxt->gyro_data.vender_div = data->vender_div;
GYRO_LOG("gyro register data path vender_div: %d\n", cxt->gyro_data.vender_div);
if(NULL == cxt->gyro_data.get_data)
{
GYRO_LOG("gyro register data path fail \n");
return -1;
}
return 0;
}
int gyro_register_control_path(struct gyro_control_path *ctl)
{
struct gyro_context *cxt = NULL;
int err =0;
cxt = gyro_context_obj;
cxt->gyro_ctl.set_delay = ctl->set_delay;
cxt->gyro_ctl.open_report_data= ctl->open_report_data;
cxt->gyro_ctl.enable_nodata = ctl->enable_nodata;
cxt->gyro_ctl.is_support_batch = ctl->is_support_batch;
if(NULL==cxt->gyro_ctl.set_delay || NULL==cxt->gyro_ctl.open_report_data
|| NULL==cxt->gyro_ctl.enable_nodata)
{
GYRO_LOG("gyro register control path fail \n");
return -1;
}
//add misc dev for sensor hal control cmd
err = gyro_misc_init(gyro_context_obj);
if(err)
{
GYRO_ERR("unable to register gyro misc device!!\n");
return -2;
}
err = sysfs_create_group(&gyro_context_obj->mdev.this_device->kobj,
&gyro_attribute_group);
if (err < 0)
{
GYRO_ERR("unable to create gyro attribute file\n");
return -3;
}
kobject_uevent(&gyro_context_obj->mdev.this_device->kobj, KOBJ_ADD);
return 0;
}
int gyro_data_report(int x, int y, int z,int status)
{
//GYRO_LOG("+gyro_data_report! %d, %d, %d, %d\n",x,y,z,status);
struct gyro_context *cxt = NULL;
int err =0;
cxt = gyro_context_obj;
input_report_abs(cxt->idev, EVENT_TYPE_GYRO_X, x);
input_report_abs(cxt->idev, EVENT_TYPE_GYRO_Y, y);
input_report_abs(cxt->idev, EVENT_TYPE_GYRO_Z, z);
input_report_abs(cxt->idev, EVENT_TYPE_GYRO_STATUS, status);
input_sync(cxt->idev);
}
static int gyro_probe(struct platform_device *pdev)
{
int err;
GYRO_LOG("+++++++++++++gyro_probe!!\n");
gyro_context_obj = gyro_context_alloc_object();
if (!gyro_context_obj)
{
err = -ENOMEM;
GYRO_ERR("unable to allocate devobj!\n");
goto exit_alloc_data_failed;
}
//init real gyroeleration driver
err = gyro_real_driver_init();
if(err)
{
GYRO_ERR("gyro real driver init fail\n");
goto real_driver_init_fail;
}
//init input dev
err = gyro_input_init(gyro_context_obj);
if(err)
{
GYRO_ERR("unable to register gyro input device!\n");
goto exit_alloc_input_dev_failed;
}
atomic_set(&(gyro_context_obj->early_suspend), 0);
gyro_context_obj->early_drv.level = EARLY_SUSPEND_LEVEL_STOP_DRAWING - 1,
gyro_context_obj->early_drv.suspend = gyro_early_suspend,
gyro_context_obj->early_drv.resume = gyro_late_resume,
register_early_suspend(&gyro_context_obj->early_drv);
GYRO_LOG("----gyro_probe OK !!\n");
return 0;
exit_hwmsen_create_attr_failed:
exit_misc_register_failed:
exit_err_sysfs:
if (err)
{
GYRO_ERR("sysfs node creation error \n");
gyro_input_destroy(gyro_context_obj);
}
real_driver_init_fail:
exit_alloc_input_dev_failed:
kfree(gyro_context_obj);
exit_alloc_data_failed:
GYRO_LOG("----gyro_probe fail !!!\n");
return err;
}
static int gyro_remove(struct platform_device *pdev)
{
GYRO_FUN(f);
int err=0;
input_unregister_device(gyro_context_obj->idev);
sysfs_remove_group(&gyro_context_obj->idev->dev.kobj,
&gyro_attribute_group);
if((err = misc_deregister(&gyro_context_obj->mdev)))
{
GYRO_ERR("misc_deregister fail: %d\n", err);
}
kfree(gyro_context_obj);
return 0;
}
static void gyro_early_suspend(struct early_suspend *h)
{
atomic_set(&(gyro_context_obj->early_suspend), 1);
GYRO_LOG(" gyro_early_suspend ok------->hwm_obj->early_suspend=%d \n",atomic_read(&(gyro_context_obj->early_suspend)));
return ;
}
/*----------------------------------------------------------------------------*/
static void gyro_late_resume(struct early_suspend *h)
{
atomic_set(&(gyro_context_obj->early_suspend), 0);
GYRO_LOG(" gyro_late_resume ok------->hwm_obj->early_suspend=%d \n",atomic_read(&(gyro_context_obj->early_suspend)));
return ;
}
static int gyro_suspend(struct platform_device *dev, pm_message_t state)
{
return 0;
}
/*----------------------------------------------------------------------------*/
static int gyro_resume(struct platform_device *dev)
{
return 0;
}
static struct platform_driver gyro_driver =
{
.probe = gyro_probe,
.remove = gyro_remove,
.suspend = gyro_suspend,
.resume = gyro_resume,
.driver =
{
.name = GYRO_PL_DEV_NAME,//mt_gyro_pl
}
};
static int __init gyro_init(void)
{
GYRO_FUN(f);
if(platform_driver_register(&gyro_driver))
{
GYRO_ERR("failed to register gyro driver\n");
return -ENODEV;
}
return 0;
}
static void __exit gyro_exit(void)
{
platform_driver_unregister(&gyro_driver);
platform_driver_unregister(&gyroscope_driver);
}
module_init(gyro_init);
module_exit(gyro_exit);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("GYROSCOPE device driver");
MODULE_AUTHOR("Mediatek");
arch/arm/mach-mt8127/ford/gyroscope/gyroscope.h
+116
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@@ -0,0 +1,116 @@
#ifndef __GYROSCOPE_H__
#define __GYROSCOPE_H__
#include <linux/wakelock.h>
#include <linux/interrupt.h>
#include <linux/miscdevice.h>
#include <linux/platform_device.h>
#include <linux/input.h>
#include <linux/workqueue.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/hwmsensor.h>
#include <linux/earlysuspend.h>
#include <linux/hwmsen_dev.h>
#define GYRO_TAG "<GYROSCOPE> "
#define GYRO_FUN(f) printk(GYRO_TAG"%s\n", __func__)
#define GYRO_ERR(fmt, args...) printk(GYRO_TAG"%s %d : "fmt, __func__, __LINE__, ##args)
#define GYRO_LOG(fmt, args...) printk(GYRO_TAG fmt, ##args)
#define GYRO_VER(fmt, args...) printk(GYRO_TAG"%s: "fmt, __func__, ##args) //((void)0)
#define OP_GYRO_DELAY 0X01
#define OP_GYRO_ENABLE 0X02
#define OP_GYRO_GET_DATA 0X04
#define GYRO_INVALID_VALUE -1
#define EVENT_TYPE_GYRO_X ABS_X
#define EVENT_TYPE_GYRO_Y ABS_Y
#define EVENT_TYPE_GYRO_Z ABS_Z
#define EVENT_TYPE_GYRO_STATUS ABS_WHEEL
#define GYRO_VALUE_MAX (32767)
#define GYRO_VALUE_MIN (-32768)
#define GYRO_STATUS_MIN (0)
#define GYRO_STATUS_MAX (64)
#define GYRO_DIV_MAX (32767)
#define GYRO_DIV_MIN (1)
#define MAX_CHOOSE_GYRO_NUM 5
struct gyro_control_path
{
int (*open_report_data)(int open);//open data rerport to HAL
int (*enable_nodata)(int en);//only enable not report event to HAL
int (*set_delay)(u64 delay);
bool is_report_input_direct;
bool is_support_batch;
};
struct gyro_data_path
{
int (*get_data)(int *x,int *y, int *z,int *status);
int vender_div;
};
struct gyro_init_info
{
char *name;
int (*init)(void);
int (*uninit)(void);
struct platform_driver* platform_diver_addr;
};
struct gyro_data{
hwm_sensor_data gyro_data ;
int data_updata;
//struct mutex lock;
};
struct gyro_drv_obj {
void *self;
int polling;
int (*gyro_operate)(void* self, uint32_t command, void* buff_in, int size_in,
void* buff_out, int size_out, int* actualout);
};
struct gyro_context {
struct input_dev *idev;
struct miscdevice mdev;
struct work_struct report;
struct mutex gyro_op_mutex;
atomic_t delay; /*polling period for reporting input event*/
atomic_t wake; /*user-space request to wake-up, used with stop*/
struct timer_list timer; /* polling timer */
atomic_t trace;
struct early_suspend early_drv;
atomic_t early_suspend;
//struct gyro_drv_obj drv_obj;
struct gyro_data drv_data;
struct gyro_control_path gyro_ctl;
struct gyro_data_path gyro_data;
bool is_active_nodata; // Active, but HAL don't need data sensor. such as orientation need
bool is_active_data; // Active and HAL need data .
bool is_first_data_after_enable;
bool is_polling_run;
bool is_batch_enable;
};
//driver API for internal
//extern int gyro_enable_nodata(int enable);
//extern int gyro_attach(struct gyro_drv_obj *obj);
//driver API for third party vendor
//for auto detect
extern int gyro_driver_add(struct gyro_init_info* obj) ;
extern int gyro_data_report(int x, int y, int z,int status);
extern int gyro_register_control_path(struct gyro_control_path *ctl);
extern int gyro_register_data_path(struct gyro_data_path *data);
#endif
arch/arm/mach-mt8127/ford/gyroscope/inc/cust_gyro.h
+23
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@@ -0,0 +1,23 @@
#ifndef __CUST_GYRO_H__
#define __CUST_GYRO_H__
#include <linux/types.h>
#define GYRO_CUST_I2C_ADDR_NUM 2
struct gyro_hw {
unsigned short addr;
int i2c_num; /*!< the i2c bus used by the chip */
int direction; /*!< the direction of the chip */
int power_id; /*!< the LDO ID of the chip, MT6516_POWER_NONE means the power is always on*/
int power_vol; /*!< the Power Voltage used by the chip */
int firlen; /*!< the length of low pass filter */
int (*power)(struct gyro_hw *hw, unsigned int on, char *devname);
unsigned char i2c_addr[GYRO_CUST_I2C_ADDR_NUM]; /*!< i2c address list,for chips which has different addresses with different HW layout */
int power_vio_id; /*!< the LDO ID of the chip, MT6516_POWER_NONE means the power is always on*/
int power_vio_vol; /*!< the Power Voltage used by the chip */
bool is_batch_supported;
};
extern struct gyro_hw* get_cust_gyro_hw(void);
#endif
arch/arm/mach-mt8127/ford/gyroscope/mpu6050.c
+1869
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File diff suppressed because it is too large Load Diff
arch/arm/mach-mt8127/ford/gyroscope/mpu6050.h
+84
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@@ -0,0 +1,84 @@
#ifndef MPU6050_H
#define MPU6050_H
#include <linux/ioctl.h>
#define MPU6050_ACCESS_BY_GSE_I2C
#ifdef MPU6050_ACCESS_BY_GSE_I2C
#define MPU6050_I2C_SLAVE_ADDR (0xD2) /* mtk i2c not allow to probe two same address */
#else
#define MPU6050_I2C_SLAVE_ADDR 0xD0
#endif
/* MPU6050 Register Map (Please refer to MPU6050 Specifications) */
#define MPU6050_REG_DEVID 0x75
#define MPU6050_REG_FIFO_EN 0x23
#define MPU6050_REG_AUX_VDD 0x01
#define MPU6050_REG_SAMRT_DIV 0x19
#define MPU6050_REG_CFG 0x1A //set external sync, full-scale range and sample rate, low pass filter bandwidth
#define MPU6050_REG_GYRO_CFG 0x1B // full-scale range and sample rate,
#define MPU6050_REG_GYRO_XH 0x43
#define MPU6050_REG_TEMPH 0x41
#define MPU6050_REG_FIFO_CNTH 0x72
#define MPU6050_REG_FIFO_CNTL 0x73
#define MPU6050_REG_FIFO_DATA 0x74
#define MPU6050_REG_FIFO_CTL 0x6A
#define MPU6050_REG_PWR_CTL 0x6B
#define MPU6050_REG_PWR_CTL2 0x6C
/*MPU6050 Register Bit definitions*/
#define MPU6050_FIFO_GYROX_EN 0x40 //insert the X Gyro data into FIFO
#define MPU6050_FIFO_GYROY_EN 0x20 //insert the Y Gyro data into FIFO
#define MPU6050_FIFO_GYROZ_EN 0x10 //insert the Z Gyro data into FIFO
#define MPU6050_AUX_VDDIO_DIS 0x00 //disable VDD level for the secondary I2C bus clock and data lines
// for MPU6050_REG_CFG
#define MPU6050_EXT_SYNC 0x03 //0x05 //captue the state of external frame sync input pin to insert into LSB of registers
#define MPU6050_SYNC_GYROX 0x02
// for MPU6050_REG_GYRO_CFG
#define MPU6050_FS_RANGE 0x03 //set the full-scale range of the gyro sensors
#define MPU6050_FS_1000 0x02
#define MPU6050_FS_1000_LSB 33
#define MPU6050_FS_MAX_LSB 131
#define MPU6050_RATE_1K_LPFB_188HZ 0x01
#define MPU6050_RATE_1K_LPFB_256HZ 0x00
#define MPU6050_FIFO_EN 0x40 //enable FIFO operation for sensor data
#define MPU6050_FIFO_RST 0x40 //reset FIFO function
#define MPU6050_SLEEP 0x40 //enable low power sleep mode
#define MPU6050_SUCCESS 0
#define MPU6050_ERR_I2C -1
#define MPU6050_ERR_STATUS -3
#define MPU6050_ERR_SETUP_FAILURE -4
#define MPU6050_ERR_GETGSENSORDATA -5
#define MPU6050_ERR_IDENTIFICATION -6
#define MPU6050_BUFSIZE 60
// 1 rad = 180/PI degree, MAX_LSB = 131,
// 180*131/PI = 7506
#define DEGREE_TO_RAD 7506
#endif //MPU6050_H
arch/arm/mach-mt8127/ford/hdmi/Makefile
Executable
+4
View File
@@ -0,0 +1,4 @@
include $(srctree)/drivers/misc/mediatek/Makefile.custom
obj-y := hdmi_cust.o
arch/arm/mach-mt8127/ford/hdmi/hdmi_cust.c
+131
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@@ -0,0 +1,131 @@
/* Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <cust_gpio_usage.h>
#include <hdmi_cust.h>
#include <mach/mt_gpio.h>
/******************************************************************
** Basic define
******************************************************************/
#ifndef s32
#define s32 signed int
#endif
#ifndef s64
#define s64 signed long long
#endif
static bool cust_power_on = false;
int cust_hdmi_power_on(int on)
{
/*
if(on > 0)
{
printk("MHL_Power power %x, rst %x \n" ,GPIO_MHL_POWER_CTRL_PIN, GPIO_MHL_RST_B_PIN);
mt_set_gpio_mode(GPIO_MHL_POWER_CTRL_PIN, GPIO_MODE_00);
mt_set_gpio_dir(GPIO_MHL_POWER_CTRL_PIN, GPIO_DIR_OUT);
mt_set_gpio_out(GPIO_MHL_POWER_CTRL_PIN, GPIO_OUT_ONE);
#ifdef PMIC_APP_MHL_POWER_LDO1
if(cust_power_on == false)
{
hwPowerOn(PMIC_APP_MHL_POWER_LDO1, VOL_1200,"MHL");
cust_power_on = true;
}
#else
printk("Error: PMIC_APP_MHL_POWER_LDO1 not defined -\n" );
#endif
}
else
{
#ifdef PMIC_APP_MHL_POWER_LDO1
if(cust_power_on == true)
{
hwPowerDown(PMIC_APP_MHL_POWER_LDO1, "MHL");
cust_power_on = false;
}
#endif
}
*/
return 0;
}
int cust_hdmi_dpi_gpio_on(int on)
{
/*
unsigned int dpi_pin_start = 0;
if(on > 0)
{
#ifdef GPIO_EXT_DISP_DPI0_PIN
for(dpi_pin_start = GPIO_EXT_DISP_DPI0_PIN; dpi_pin_start < GPIO_EXT_DISP_DPI0_PIN + 16; dpi_pin_start++)
{
mt_set_gpio_mode(dpi_pin_start, GPIO_MODE_01);
}
printk("%s, %d GPIO_EXT_DISP_DPI0_PIN is defined+ %x\n", __func__, __LINE__, GPIO_EXT_DISP_DPI0_PIN);
#else
printk("%s,%d Error: GPIO_EXT_DISP_DPI0_PIN is not defined\n", __func__, __LINE__);
#endif
}
else
{
#ifdef GPIO_EXT_DISP_DPI0_PIN
for(dpi_pin_start = GPIO_EXT_DISP_DPI0_PIN; dpi_pin_start < GPIO_EXT_DISP_DPI0_PIN + 16; dpi_pin_start++)
{
mt_set_gpio_mode(dpi_pin_start, GPIO_MODE_00);
mt_set_gpio_dir(dpi_pin_start, GPIO_DIR_IN);
mt_set_gpio_pull_enable(dpi_pin_start, GPIO_PULL_ENABLE);
mt_set_gpio_pull_select(dpi_pin_start, GPIO_PULL_DOWN);
}
printk("%s, %d GPIO_EXT_DISP_DPI0_PIN is defined- %x\n", __func__, __LINE__, GPIO_EXT_DISP_DPI0_PIN);
#endif
}
*/
return 0;
}
int cust_hdmi_i2s_gpio_on(int on)
{
/*
if(on > 0)
{
#ifdef GPIO_MHL_I2S_OUT_WS_PIN
mt_set_gpio_mode(GPIO_MHL_I2S_OUT_WS_PIN, GPIO_MHL_I2S_OUT_WS_PIN_M_I2S3_WS);
mt_set_gpio_mode(GPIO_MHL_I2S_OUT_CK_PIN, GPIO_MHL_I2S_OUT_CK_PIN_M_I2S3_BCK);
mt_set_gpio_mode(GPIO_MHL_I2S_OUT_DAT_PIN, GPIO_MHL_I2S_OUT_DAT_PIN_M_I2S3_DO);
#else
printk("%s,%d Error. GPIO_MHL_I2S_OUT_WS_PIN is not defined\n", __func__, __LINE__);
#endif
}
else
{
#ifdef GPIO_MHL_I2S_OUT_WS_PIN
mt_set_gpio_pull_enable(GPIO_MHL_I2S_OUT_WS_PIN, GPIO_PULL_DISABLE);
mt_set_gpio_pull_enable(GPIO_MHL_I2S_OUT_CK_PIN, GPIO_PULL_DISABLE);
mt_set_gpio_pull_enable(GPIO_MHL_I2S_OUT_DAT_PIN, GPIO_PULL_DISABLE);
#endif
}
*/
return 0;
}
int get_hdmi_i2c_addr(void)
{
// return (SII_I2C_ADDR);
return 0;
}
int get_hdmi_i2c_channel(void)
{
// return (HDMI_I2C_CHANNEL);
return 0;
}
arch/arm/mach-mt8127/ford/hdmi/hdmi_cust.h
+47
View File
@@ -0,0 +1,47 @@
/* Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef HDMI_CUSTOMIZATION_H
#define HDMI_CUSTOMIZATION_H
/******************************************************************
** scale adjustment
******************************************************************/
/*
#define USING_SCALE_ADJUSTMENT
///if mhl chip CI2CA pin is pull up, the folloing should be defined. otherwise, please mask it.
#define SII_I2C_ADDR (0x72)
#define HDMI_I2C_CHANNEL 3
*/
/******************************************************************
** MHL GPIO Customization
******************************************************************/
//#define MHL_PHONE_GPIO_REUSAGE
void ChangeGPIOToI2S();
void ChangeI2SToGPIO();
int cust_hdmi_power_on(int on);
int cust_hdmi_dpi_gpio_on(int on);
int cust_hdmi_i2s_gpio_on(int on);
int get_hdmi_i2c_addr(void);
int get_hdmi_i2c_channel(void);
#endif
arch/arm/mach-mt8127/ford/hdmi/inc/hdmi_drv.h
+226
View File
@@ -0,0 +1,226 @@
#ifndef __HDMI_DRV_H__
#define __HDMI_DRV_H__
#ifdef CONFIG_MTK_MT8193_HDMI_SUPPORT
#include "mt8193hdmictrl.h"
#include "mt8193edid.h"
#include "mt8193cec.h"
#define AVD_TMR_ISR_TICKS 5
#define MDI_BOUCING_TIMING 50//20 //20ms
typedef enum
{
HDMI_CEC_CMD=0,
HDMI_PLUG_DETECT_CMD,
HDMI_HDCP_PROTOCAL_CMD,
HDMI_DISABLE_HDMI_TASK_CMD,
MAX_HDMI_TMR_NUMBER
}HDMI_TASK_COMMAND_TYPE_T;
#endif
#ifndef ARY_SIZE
#define ARY_SIZE(x) (sizeof((x)) / sizeof((x[0])))
#endif
typedef enum
{
HDMI_POLARITY_RISING = 0,
HDMI_POLARITY_FALLING = 1
}HDMI_POLARITY;
typedef enum
{
HDMI_CLOCK_PHASE_0 = 0,
HDMI_CLOCK_PHASE_90 = 1
}HDMI_CLOCK_PHASE;
typedef enum
{
HDMI_COLOR_ORDER_RGB = 0,
HDMI_COLOR_ORDER_BGR = 1
}HDMI_COLOR_ORDER;
typedef enum
{
IO_DRIVING_CURRENT_8MA = (1 << 0),
IO_DRIVING_CURRENT_4MA = (1 << 1),
IO_DRIVING_CURRENT_2MA = (1 << 2),
IO_DRIVING_CURRENT_SLEW_CNTL = (1 << 3),
}IO_DRIVING_CURRENT;
#if !defined(CONFIG_MTK_MT8193_HDMI_SUPPORT)
typedef enum
{
HDMI_VIDEO_720x480p_60Hz = 0,
HDMI_VIDEO_1280x720p_60Hz =2,
HDMI_VIDEO_1920x1080p_30Hz =6,
HDMI_VIDEO_RESOLUTION_NUM
}HDMI_VIDEO_RESOLUTION;
#endif
typedef enum
{
HDMI_VIN_FORMAT_RGB565,
HDMI_VIN_FORMAT_RGB666,
HDMI_VIN_FORMAT_RGB888,
} HDMI_VIDEO_INPUT_FORMAT;
typedef enum
{
HDMI_VOUT_FORMAT_RGB888,
HDMI_VOUT_FORMAT_YUV422,
HDMI_VOUT_FORMAT_YUV444,
}HDMI_VIDEO_OUTPUT_FORMAT;
typedef enum
{
HDMI_AUDIO_PCM_16bit_48000,
HDMI_AUDIO_PCM_16bit_44100,
HDMI_AUDIO_PCM_16bit_32000,
HDMI_AUDIO_SOURCE_STREAM,
}HDMI_AUDIO_FORMAT;
typedef struct
{
HDMI_VIDEO_RESOLUTION vformat;
HDMI_VIDEO_INPUT_FORMAT vin;
HDMI_VIDEO_OUTPUT_FORMAT vout;
HDMI_AUDIO_FORMAT aformat;
}HDMI_CONFIG;
typedef enum{
HDMI_OUTPUT_MODE_LCD_MIRROR,
HDMI_OUTPUT_MODE_VIDEO_MODE,
HDMI_OUTPUT_MODE_DPI_BYPASS
}HDMI_OUTPUT_MODE;
typedef enum{
HDMI_CABLE,
MHL_CABLE,
MHL_SMB_CABLE,
MHL_2_CABLE ///MHL 2.0
}HDMI_CABLE_TYPE;
typedef struct
{
unsigned int width;
unsigned int height;
HDMI_CONFIG init_config;
/* polarity parameters */
HDMI_POLARITY clk_pol;
HDMI_POLARITY de_pol;
HDMI_POLARITY vsync_pol;
HDMI_POLARITY hsync_pol;
/* timing parameters */
unsigned int hsync_pulse_width;
unsigned int hsync_back_porch;
unsigned int hsync_front_porch;
unsigned int vsync_pulse_width;
unsigned int vsync_back_porch;
unsigned int vsync_front_porch;
/* output format parameters */
HDMI_COLOR_ORDER rgb_order;
/* intermediate buffers parameters */
unsigned int intermediat_buffer_num; // 2..3
/* iopad parameters */
IO_DRIVING_CURRENT io_driving_current;
HDMI_OUTPUT_MODE output_mode;
int is_force_awake;
int is_force_landscape;
unsigned int scaling_factor; // determine the scaling of output screen size, valid value 0~10
// 0 means no scaling, 5 means scaling to 95%, 10 means 90%
HDMI_CABLE_TYPE cabletype;
bool NeedSwHDCP;
}HDMI_PARAMS;
typedef enum{
HDMI_STATE_NO_DEVICE,
HDMI_STATE_ACTIVE,
HDMI_STATE_CONNECTING,
#if defined(CONFIG_MTK_MT8193_HDMI_SUPPORT)
HDMI_STATE_PLUGIN_ONLY,
HDMI_STATE_EDID_UPDATE,
HDMI_STATE_CEC_UPDATE
#endif
}HDMI_STATE;
// ---------------------------------------------------------------------------
typedef struct
{
void (*set_reset_pin)(unsigned int value);
int (*set_gpio_out)(unsigned int gpio, unsigned int value);
void (*udelay)(unsigned int us);
void (*mdelay)(unsigned int ms);
void (*wait_transfer_done)(void);
void (*state_callback)(HDMI_STATE state);
}HDMI_UTIL_FUNCS;
typedef struct
{
void (*set_util_funcs)(const HDMI_UTIL_FUNCS *util);
void (*get_params)(HDMI_PARAMS *params);
int (*init)(void);
int (*enter)(void);
int (*exit)(void);
void (*suspend)(void);
void (*resume)(void);
int (*audio_config)(HDMI_AUDIO_FORMAT aformat);
int (*video_config)(HDMI_VIDEO_RESOLUTION vformat, HDMI_VIDEO_INPUT_FORMAT vin, HDMI_VIDEO_OUTPUT_FORMAT vou);
int (*video_enable)(bool enable);
int (*audio_enable)(bool enable);
int (*irq_enable)(bool enable);
int (*power_on)(void);
void (*power_off)(void);
HDMI_STATE (*get_state)(void);
void (*set_mode)(unsigned char ucMode);
void (*dump)(void);
#if !defined(CONFIG_MTK_MT8193_HDMI_SUPPORT)
void (*read)(unsigned char u8Reg);
void (*write)(unsigned char u8Reg, unsigned char u8Data);
void (*log_enable)(bool enable);
#else
void (*read)(u16 u2Reg, u32 *p4Data);
void (*write)(u16 u2Reg, u32 u4Data);
void (*log_enable)(u16 enable);
void (*InfoframeSetting)(u8 i1typemode, u8 i1typeselect);
void (*checkedid)(u8 i1noedid);
void (*colordeep)(u8 u1colorspace, u8 u1deepcolor);
void (*enablehdcp)(u8 u1hdcponoff);
void (*setcecrxmode)(u8 u1cecrxmode);
void (*hdmistatus)(void);
void (*hdcpkey)(u8 *pbhdcpkey);
void (*getedid)(HDMI_EDID_INFO_T *pv_get_info);
void (*setcecla)(CEC_DRV_ADDR_CFG_T* prAddr);
void (*sendsltdata)(u8 *pu1Data);
void (*getceccmd)(CEC_FRAME_DESCRIPTION* frame);
void (*getsltdata)(CEC_SLT_DATA* rCecSltData);
void (*setceccmd)(CEC_SEND_MSG_T* msg);
void (*cecenable)(u8 u1EnCec);
void (*getcecaddr)(CEC_ADDRESS *cecaddr);
void (*mutehdmi)(u8 u1flagvideomute, u8 u1flagaudiomute);
#endif
} HDMI_DRIVER;
// ---------------------------------------------------------------------------
// HDMI Driver Functions
// ---------------------------------------------------------------------------
const HDMI_DRIVER* HDMI_GetDriver(void);
#endif // __HDMI_DRV_H__
arch/arm/mach-mt8127/ford/headset/Makefile
Executable
+4
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@@ -0,0 +1,4 @@
include $(srctree)/drivers/misc/mediatek/Makefile.custom
obj-y := accdet_custom.o
arch/arm/mach-mt8127/ford/headset/accdet_custom.c
+28
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@@ -0,0 +1,28 @@
#include "accdet_custom_def.h"
#include <accdet_custom.h>
//key press customization: long press time
struct headset_key_custom headset_key_custom_setting = {
2000
};
struct headset_key_custom* get_headset_key_custom_setting(void)
{
return &headset_key_custom_setting;
}
#ifdef ACCDET_MULTI_KEY_FEATURE
static struct headset_mode_settings cust_headset_settings = {
0x900, 0x900, 1, 0x3f0, 0x800, 0x800, 0x20
};
#else
//headset mode register settings(for MT6575)
static struct headset_mode_settings cust_headset_settings = {
0x900, 0x400, 1, 0x3f0, 0x3000, 0x3000, 0x20
};
#endif
struct headset_mode_settings* get_cust_headset_settings(void)
{
return &cust_headset_settings;
}
arch/arm/mach-mt8127/ford/headset/accdet_custom.h
+14
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@@ -0,0 +1,14 @@
struct headset_mode_settings{
int pwm_width; //pwm frequence
int pwm_thresh; //pwm duty
int fall_delay; //falling stable time
int rise_delay; //rising stable time
int debounce0; //hook switch or double check debounce
int debounce1; //mic bias debounce
int debounce3; //plug out debounce
};
//key press customization: long press time
struct headset_key_custom{
int headset_long_press_time;
};
arch/arm/mach-mt8127/ford/headset/accdet_custom_def.h
+15
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@@ -0,0 +1,15 @@
// use accdet + EINT solution
#define ACCDET_EINT
// support multi_key feature
#define ACCDET_MULTI_KEY_FEATURE
// after 5s disable accdet
#define ACCDET_LOW_POWER
//#define ACCDET_PIN_RECOGNIZATION
#define ACCDET_28V_MODE
#define ACCDET_SHORT_PLUGOUT_DEBOUNCE
#define ACCDET_SHORT_PLUGOUT_DEBOUNCE_CN 20
//extern struct headset_mode_settings* get_cust_headset_settings(void);
//extern int get_long_press_time_cust(void);
arch/arm/mach-mt8127/ford/keypad/Makefile
Executable
+3
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@@ -0,0 +1,3 @@
include $(srctree)/drivers/misc/mediatek/Makefile.custom
obj-y := mtk_kpd_bkl.o
arch/arm/mach-mt8127/ford/keypad/mtk_kpd.h
+93
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@@ -0,0 +1,93 @@
/*
* Copyright (C) 2010 MediaTek, Inc.
*
* Author: Terry Chang <terry.chang@mediatek.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef _MTK_KPD_H_
#define _MTK_KPD_H_
#include <linux/kernel.h>
#include <cust_kpd.h>
#include <mach/mt_pm_ldo.h>
#include <linux/delay.h>
/* include PMIC header file */
#include <mach/mt_typedefs.h>
#include <mach/pmic_mt6329_hw_bank1.h>
#include <mach/pmic_mt6329_sw_bank1.h>
#include <mach/pmic_mt6329_hw.h>
#include <mach/pmic_mt6329_sw.h>
#include <mach/pmic_mt6320_sw.h>
#include <mach/upmu_common_sw.h>
#include <mach/upmu_hw.h>
#define KPD_PWRKEY_MAP KEY_POWER
#define KPD_PWRKEY_USE_EINT KPD_NO
#define KPD_PWRKEY_USE_PMIC KPD_YES
#define KPD_DRV_CTRL_BACKLIGHT KPD_NO /* retired, move to Lights framework */
#define KPD_BACKLIGHT_TIME 8 /* sec */
/* the keys can wake up the system and we should enable backlight */
#define KPD_BACKLIGHT_WAKE_KEY \
{ \
KEY_ENDCALL, KEY_POWER, \
}
#ifdef CONFIG_MTK_HALL_SENSOR
#define KPD_HAS_SLIDE_QWERTY KPD_YES
#else
#define KPD_HAS_SLIDE_QWERTY KPD_No
#endif
#if 0
static inline bool powerOn_slidePin_interface() {
return hwPowerOn(MT65XX_POWER_LDO_VCAM_IO, VOL_2800, "Qwerty slide");
}
static inline bool powerOff_slidePin_interface(){
return hwPowerDown(MT65XX_POWER_LDO_VCAM_IO, "Qwerty slide");
}
#endif
#define CUST_EINT_KPD_SLIDE_POLARITY 0
#define KPD_SLIDE_EINT CUST_EINT_KPD_SLIDE_NUM
#define KPD_SLIDE_DEBOUNCE CUST_EINT_KPD_SLIDE_DEBOUNCE_CN /* ms */
#define KPD_SLIDE_POLARITY CUST_EINT_KPD_SLIDE_POLARITY
#define KPD_SLIDE_SENSITIVE CUST_EINT_KPD_SLIDE_SENSITIVE
#if KPD_DRV_CTRL_BACKLIGHT
extern void kpd_enable_backlight(void);
extern void kpd_disable_backlight(void);
extern void kpd_backlight_handler(bool pressed, u16 linux_keycode);
#else
#define kpd_enable_backlight() do {} while (0)
#define kpd_disable_backlight() do {} while (0)
#define kpd_backlight_handler(pressed, linux_keycode) do {} while (0)
#endif
/* for META tool */
extern void kpd_set_backlight(bool onoff, void *val1, void *val2);
#if KPD_PWRKEY_USE_PMIC
void kpd_pwrkey_pmic_handler(unsigned long pressed);
#else
static inline void kpd_pwrkey_pmic_handler(unsigned long data){}
#endif
void kpd_pmic_rstkey_handler(unsigned long pressed);
#define ONEKEY_REBOOT_NORMAL_MODE
//#define TWOKEY_REBOOT_NORMAL_MODE
#define ONEKEY_REBOOT_OTHER_MODE
//#define TWOKEY_REBOOT_OTHER_MODE
#define KPD_PMIC_RSTKEY_MAP KEY_VOLUMEDOWN
#define KPD_PMIC_LPRST_TD 1 /* timeout period. 0: 7sec; 1: 11sec; 2: 14sec; 3: 5sec */
#endif
arch/arm/mach-mt8127/ford/keypad/mtk_kpd_bkl.c
+52
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@@ -0,0 +1,52 @@
/*
* Copyright (C) 2010 MediaTek, Inc.
*
* Author: Terry Chang <terry.chang@mediatek.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <mach/mt_typedefs.h>
#include <mtk_kpd.h> /* custom file */
#if KPD_DRV_CTRL_BACKLIGHT
void kpd_enable_backlight(void)
{
/*mt6326_kpled_dim_duty_Full();
mt6326_kpled_Enable();*/
}
void kpd_disable_backlight(void)
{
/*mt6326_kpled_dim_duty_0();
mt6326_kpled_Disable();*/
}
#endif
/* for META tool */
void kpd_set_backlight(bool onoff, void *val1, void *val2)
{
/*u8 div = *(u8 *)val1;
u8 duty = *(u8 *)val2;
if (div > 15)
div = 15;
pmic_kp_dim_div(div);
if (duty > 31)
duty = 31;
pmic_kp_dim_duty(duty);
if (onoff)
mt6326_kpled_Enable();
else
mt6326_kpled_Disable();*/
}
arch/arm/mach-mt8127/ford/lcm/CPT_CLAP070WP03XG_LVDS.c
+391
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@@ -0,0 +1,391 @@
#ifndef BUILD_LK
#include <linux/string.h>
#endif
#ifdef BUILD_LK
#include <platform/mt_gpio.h>
#include <platform/mt_pmic.h>
#include <debug.h>
#include <platform/upmu_common.h>
#elif (defined BUILD_UBOOT)
#include <asm/arch/mt6577_gpio.h>
#else
#include <mach/mt_gpio.h>
#include <linux/xlog.h>
#include <mach/mt_pm_ldo.h>
#endif
#include "lcm_drv.h"
#include "mt8193_lvds.h"
// ---------------------------------------------------------------------------
// Local Constants
// ---------------------------------------------------------------------------
#if defined(MTK_ALPS_BOX_SUPPORT)
/*for 8127 box hdmi main path */
#define FRAME_WIDTH (1920)
#define FRAME_HEIGHT (1080)
#else
#define FRAME_WIDTH (800)
#define FRAME_HEIGHT (1280)
#endif
//#define GPIO_LCD_RST_EN GPIO90
//#define GPIO_LCD_STB_EN GPIO89
#ifdef GPIO_LCM_PWR
#define GPIO_LCD_PWR GPIO_LCM_PWR
#else
#define GPIO_LCD_PWR 0xFFFFFFFF
#endif
#ifdef GPIO_LCM_PWR_EN
#define GPIO_LCD_PWR_EN GPIO_LCM_PWR_EN
#else
#define GPIO_LCD_PWR_EN 0xFFFFFFFF
#endif
#ifdef GPIO_LCM_PWR2_EN
#define GPIO_LCD_PWR2_EN GPIO_LCM_PWR2_EN
#else
#define GPIO_LCD_PWR2_EN 0xFFFFFFFF
#endif
#ifdef GPIO_LCM_RST
#define GPIO_LCD_RST_EN GPIO_LCM_RST
#else
#define GPIO_LCD_RST_EN 0xFFFFFFFF
#endif
#ifdef GPIO_LCM_STB
#define GPIO_LCD_STB_EN GPIO_LCM_STB
#else
#define GPIO_LCD_STB_EN 0xFFFFFFFF
#endif
#ifdef GPIO_LCM_LVL_SHIFT_EN
#define GPIO_SHIFT_EN GPIO_LCM_LVL_SHIFT_EN
#else
#define GPIO_SHIFT_EN 0xFFFFFFFF
#endif
#ifdef GPIO_LCM_BL_EN
#define GPIO_LCD_BL_EN GPIO_LCM_BL_EN
#else
#define GPIO_LCD_BL_EN 0xFFFFFFFF
#endif
#ifdef GPIO_LCM_BRIDGE_EN
#define GPIO_LCD_BRIDGE_EN GPIO_LCM_BRIDGE_EN
#else
#define GPIO_LCD_BRIDGE_EN 0xFFFFFFFF
#endif
#define HSYNC_PULSE_WIDTH 16
#define HSYNC_BACK_PORCH 16
#define HSYNC_FRONT_PORCH 32
#define VSYNC_PULSE_WIDTH 2
#define VSYNC_BACK_PORCH 2
#define VSYNC_FRONT_PORCH 4
// ---------------------------------------------------------------------------
// Local Variables
// ---------------------------------------------------------------------------
static LCM_UTIL_FUNCS lcm_util = {0};
#define SET_RESET_PIN(v) (mt_set_reset_pin((v)))
#define UDELAY(n)
#define MDELAY(n)
// ---------------------------------------------------------------------------
// Local Functions
// ---------------------------------------------------------------------------
static __inline void send_ctrl_cmd(unsigned int cmd)
{
}
static __inline void send_data_cmd(unsigned int data)
{
}
static __inline void set_lcm_register(unsigned int regIndex,
unsigned int regData)
{
}
static void lcm_set_gpio_output(unsigned int GPIO, unsigned int output)
{
if(GPIO == 0xFFFFFFFF)
{
#ifdef BUILD_LK
printf("[LK/LCM] GPIO_LCD_PWR = 0x%x \n",GPIO_LCD_PWR);
printf("[LK/LCM] GPIO_LCD_PWR_EN = 0x%x\n",GPIO_LCD_PWR_EN);
printf("[LK/LCM] GPIO_LCD_PWR2_EN = 0x%x \n",GPIO_LCD_PWR2_EN);
printf("[LK/LCM] GPIO_LCD_RST_EN = 0x%x \n",GPIO_LCD_RST_EN);
printf("[LK/LCM] GPIO_LCD_STB_EN = 0x%x\n",GPIO_LCD_STB_EN);
printf("[LK/LCM] GPIO_SHIFT_EN = 0x%x\n",GPIO_SHIFT_EN);
printf("[LK/LCM] GPIO_LCD_BL_EN = 0x%x\n",GPIO_LCD_BL_EN);
printf("[LK/LCM] GPIO_LCD_BRIDGE_EN = 0x%x \n",GPIO_LCD_BRIDGE_EN);
#elif (defined BUILD_UBOOT)
// do nothing in uboot
#else
//printf("kernel] lcm_set gpio() \n");
#endif
return;
}
mt_set_gpio_mode(GPIO, GPIO_MODE_00);
mt_set_gpio_dir(GPIO, GPIO_DIR_OUT);
mt_set_gpio_out(GPIO, (output>0)? GPIO_OUT_ONE: GPIO_OUT_ZERO);
}
// ---------------------------------------------------------------------------
// LCM Driver Implementations
// ---------------------------------------------------------------------------
static void lcm_set_util_funcs(const LCM_UTIL_FUNCS *util)
{
memcpy(&lcm_util, util, sizeof(LCM_UTIL_FUNCS));
}
static void lcm_get_params(LCM_PARAMS *params)
{
memset(params, 0, sizeof(LCM_PARAMS));
params->type = LCM_TYPE_DPI;
params->ctrl = LCM_CTRL_SERIAL_DBI;
params->width = FRAME_WIDTH;
params->height = FRAME_HEIGHT;
params->io_select_mode = 0;
params->dpi.PLL_CLOCK = 67; //67MHz
/* RGB interface configurations */
params->dpi.mipi_pll_clk_ref = 0;
params->dpi.mipi_pll_clk_div1 = 0x80000101; //lvds pll 65M
params->dpi.mipi_pll_clk_div2 = 0x800a0000;
//params->dpi.dpi_clk_div = 2;
//params->dpi.dpi_clk_duty = 1;
params->dpi.clk_pol = LCM_POLARITY_FALLING;
params->dpi.de_pol = LCM_POLARITY_RISING;
params->dpi.vsync_pol = LCM_POLARITY_FALLING;
params->dpi.hsync_pol = LCM_POLARITY_FALLING;
params->dpi.hsync_pulse_width = HSYNC_PULSE_WIDTH;
params->dpi.hsync_back_porch = HSYNC_BACK_PORCH;
params->dpi.hsync_front_porch = HSYNC_FRONT_PORCH;
params->dpi.vsync_pulse_width = VSYNC_PULSE_WIDTH;
params->dpi.vsync_back_porch = VSYNC_BACK_PORCH;
params->dpi.vsync_front_porch = VSYNC_FRONT_PORCH;
//params->dpi.i2x_en = 1;
params->dpi.lvds_tx_en = 1;
params->dpi.ssc_disable = 1;
params->dpi.format = LCM_DPI_FORMAT_RGB888; // format is 24 bit
params->dpi.rgb_order = LCM_COLOR_ORDER_RGB;
params->dpi.is_serial_output = 0;
params->dpi.intermediat_buffer_num = 0;
params->dpi.io_driving_current = LCM_DRIVING_CURRENT_2MA;
}
static void lcm_init(void)
{
#ifdef BUILD_LK
printf("[LK/LCM] lcm_init() enter\n");
lcm_set_gpio_output(GPIO_LCD_PWR, 1);
lcm_set_gpio_output(GPIO_LCD_PWR_EN, 0);
lcm_set_gpio_output(GPIO_LCD_PWR2_EN, 1);
//VGP6 3.3V
//pmic_config_interface(0x424, 0x1, 0x1, 15);
//pmic_config_interface(0x45a, 0x07, 0x07, 5);
#ifdef CONFIG_MTK_PMIC_MT6397
upmu_set_rg_vgp6_vosel(0x7);
upmu_set_rg_vgp6_sw_en(0x1);
#else
upmu_set_rg_vgp1_vosel(0x7);
upmu_set_rg_vgp1_en(0x1);
#endif
//hwPowerOn(MT65XX_POWER_LDO_VGP6, VOL_3300, "LCM");
lcm_set_gpio_output(GPIO_LCD_RST_EN,GPIO_OUT_ONE);
MDELAY(20);
lcm_set_gpio_output(GPIO_LCD_STB_EN,GPIO_OUT_ONE);
MDELAY(20);
lcm_set_gpio_output(GPIO_LCD_BL_EN, GPIO_OUT_ONE);
#elif (defined BUILD_UBOOT)
// do nothing in uboot
#else
printk("[LCM] lcm_init() enter\n");
lcm_set_gpio_output(GPIO_LCD_RST_EN,GPIO_OUT_ONE);
MDELAY(20);
lcm_set_gpio_output(GPIO_LCD_STB_EN,GPIO_OUT_ONE);
MDELAY(20);
lcm_set_gpio_output(GPIO_LCD_BL_EN, GPIO_OUT_ONE);
#endif
}
static void lcm_suspend(void)
{
#ifdef BUILD_LK
printf("[LK/LCM] lcm_suspend() enter\n");
lcm_set_gpio_output(GPIO_LCD_BL_EN, 0);
MDELAY(20);
lcm_set_gpio_output(GPIO_LCD_RST_EN,GPIO_OUT_ZERO);
lcm_set_gpio_output(GPIO_LCD_STB_EN,GPIO_OUT_ZERO);
lcm_set_gpio_output(GPIO_LCD_PWR, 0);
lcm_set_gpio_output(GPIO_LCD_PWR_EN, 0);
lcm_set_gpio_output(GPIO_LCD_PWR2_EN, 0);
MDELAY(20);
#elif (defined BUILD_UBOOT)
// do nothing in uboot
#else
printk("[LCM] lcm_suspend() enter\n");
lcm_set_gpio_output(GPIO_LCD_BL_EN, 0);
MDELAY(20);
lcm_set_gpio_output(GPIO_LCD_RST_EN,GPIO_OUT_ZERO);
lcm_set_gpio_output(GPIO_LCD_STB_EN,GPIO_OUT_ZERO);
lcm_set_gpio_output(GPIO_LCD_PWR, 0);
lcm_set_gpio_output(GPIO_LCD_PWR_EN, 0);
lcm_set_gpio_output(GPIO_LCD_PWR2_EN, 0);
MDELAY(20);
#ifdef CONFIG_MTK_PMIC_MT6397
hwPowerDown(MT65XX_POWER_LDO_VGP6, "LCM");//
#else
hwPowerDown(MT6323_POWER_LDO_VGP1, "LCM");//
#endif
MDELAY(20);
#endif
}
static void lcm_resume(void)
{
#ifdef BUILD_LK
printf("[LK/LCM] lcm_resume() enter\n");
//VGP6 3.3V
#ifdef CONFIG_MTK_PMIC_MT6397
upmu_set_rg_vgp6_vosel(0x7);
upmu_set_rg_vgp6_sw_en(0x1);
#else
upmu_set_rg_vgp1_vosel(0x7);
upmu_set_rg_vgp1_en(0x1);
#endif
//pmic_config_interface(0x424, 0x1, 0x1, 15);
//pmic_config_interface(0x45a, 0x07, 0x07, 5);
// hwPowerOn(MT65XX_POWER_LDO_VGP6, VOL_3300, "LCM");
lcm_set_gpio_output(GPIO_LCD_STB_EN,GPIO_OUT_ONE);
MDELAY(20);
lcm_set_gpio_output(GPIO_LCD_PWR, 1);
lcm_set_gpio_output(GPIO_LCD_PWR_EN, 1);
lcm_set_gpio_output(GPIO_LCD_PWR2_EN, 1);
MDELAY(5);
lcm_set_gpio_output(GPIO_LCD_RST_EN,GPIO_OUT_ONE);
MDELAY(20);
lcm_set_gpio_output(GPIO_LCD_BL_EN, 1);
#elif (defined BUILD_UBOOT)
// do nothing in uboot
#else
printk("[LCM] lcm_resume() enter\n");
#ifdef CONFIG_MTK_PMIC_MT6397
hwPowerOn(MT65XX_POWER_LDO_VGP6, VOL_3300, "LCM");
#else
hwPowerOn(MT6323_POWER_LDO_VGP1, VOL_3300, "LCM");
#endif
lcm_set_gpio_output(GPIO_LCD_PWR, 1);
lcm_set_gpio_output(GPIO_LCD_PWR_EN, 1);
lcm_set_gpio_output(GPIO_LCD_PWR2_EN, 1);
MDELAY(5);
lcm_set_gpio_output(GPIO_LCD_STB_EN, 1);
MDELAY(5);
lcm_set_gpio_output(GPIO_LCD_RST_EN, 1);
MDELAY(20);
lcm_set_gpio_output(GPIO_LCD_BL_EN, 1);
#endif
}
LCM_DRIVER cpt_clap070wp03xg_lvds_lcm_drv =
{
.name = "cpt_clap070wp03xg_lvds",
.set_util_funcs = lcm_set_util_funcs,
.get_params = lcm_get_params,
.init = lcm_init,
.suspend = lcm_suspend,
.resume = lcm_resume,
};
arch/arm/mach-mt8127/ford/lcm/Makefile
Executable
+4
View File
@@ -0,0 +1,4 @@
include $(srctree)/drivers/misc/mediatek/Makefile.custom
obj-y := CPT_CLAP070WP03XG_LVDS.o
obj-y += mt65xx_lcm_list.o
arch/arm/mach-mt8127/ford/lcm/inc/lcm_drv.h
+634
View File
@@ -0,0 +1,634 @@
#ifndef __LCM_DRV_H__
#define __LCM_DRV_H__
// ---------------------------------------------------------------------------
#ifndef ARY_SIZE
#define ARY_SIZE(x) (sizeof((x)) / sizeof((x[0])))
#endif
// ---------------------------------------------------------------------------
/* common enumerations */
typedef enum
{
LCM_TYPE_DBI = 0,
LCM_TYPE_DPI,
LCM_TYPE_DSI
} LCM_TYPE;
typedef enum
{
LCM_CTRL_NONE = 0,
LCM_CTRL_SERIAL_DBI,
LCM_CTRL_PARALLEL_DBI,
LCM_CTRL_GPIO
} LCM_CTRL;
typedef enum
{
LCM_POLARITY_RISING = 0,
LCM_POLARITY_FALLING = 1
} LCM_POLARITY;
typedef enum
{
LCM_CLOCK_PHASE_0 = 0,
LCM_CLOCK_PHASE_90 = 1
} LCM_CLOCK_PHASE;
typedef enum
{
LCM_COLOR_ORDER_RGB = 0,
LCM_COLOR_ORDER_BGR = 1
} LCM_COLOR_ORDER;
typedef enum
{
LCM_DRIVING_CURRENT_DEFAULT,
LCM_DRIVING_CURRENT_8MA = (1 << 0),
LCM_DRIVING_CURRENT_4MA = (1 << 1),
LCM_DRIVING_CURRENT_2MA = (1 << 2),
LCM_DRIVING_CURRENT_SLEW_CNTL = (1 << 3),
LCM_DRIVING_CURRENT_6575_4MA = (1 << 4),
LCM_DRIVING_CURRENT_6575_8MA = (3 << 4),
LCM_DRIVING_CURRENT_6575_12MA = (2 << 4),
LCM_DRIVING_CURRENT_6575_16MA = (4 << 4),
LCM_DRIVING_CURRENT_6MA,
LCM_DRIVING_CURRENT_12MA,
LCM_DRIVING_CURRENT_16MA
} LCM_DRIVING_CURRENT;
typedef enum{
LCM_INTERFACE_NOTDEFINED = 0,
LCM_INTERFACE_DSI0,
LCM_INTERFACE_DSI1,
LCM_INTERFACE_DSI_DUAL,
LCM_INTERFACE_DPI0,
LCM_INTERFACE_DPI1,
LCM_INTERFACE_DBI0
}LCM_INTERFACE_ID;
typedef enum{
LCM_IOCTL_NULL = 0,
}LCM_IOCTL;
/* DBI related enumerations */
typedef enum
{
LCM_DBI_CLOCK_FREQ_104M = 0,
LCM_DBI_CLOCK_FREQ_52M,
LCM_DBI_CLOCK_FREQ_26M,
LCM_DBI_CLOCK_FREQ_13M,
LCM_DBI_CLOCK_FREQ_7M
} LCM_DBI_CLOCK_FREQ;
typedef enum
{
LCM_DBI_DATA_WIDTH_8BITS = 0,
LCM_DBI_DATA_WIDTH_9BITS = 1,
LCM_DBI_DATA_WIDTH_16BITS = 2,
LCM_DBI_DATA_WIDTH_18BITS = 3,
LCM_DBI_DATA_WIDTH_24BITS = 4,
LCM_DBI_DATA_WIDTH_32BITS = 5
} LCM_DBI_DATA_WIDTH;
typedef enum
{
LCM_DBI_CPU_WRITE_8_BITS = 8,
LCM_DBI_CPU_WRITE_16_BITS = 16,
LCM_DBI_CPU_WRITE_32_BITS = 32,
} LCM_DBI_CPU_WRITE_BITS;
typedef enum
{
LCM_DBI_FORMAT_RGB332 = 0,
LCM_DBI_FORMAT_RGB444 = 1,
LCM_DBI_FORMAT_RGB565 = 2,
LCM_DBI_FORMAT_RGB666 = 3,
LCM_DBI_FORMAT_RGB888 = 4
} LCM_DBI_FORMAT;
typedef enum
{
LCM_DBI_TRANS_SEQ_MSB_FIRST = 0,
LCM_DBI_TRANS_SEQ_LSB_FIRST = 1
} LCM_DBI_TRANS_SEQ;
typedef enum
{
LCM_DBI_PADDING_ON_LSB = 0,
LCM_DBI_PADDING_ON_MSB = 1
} LCM_DBI_PADDING;
typedef enum
{
LCM_DBI_TE_MODE_DISABLED = 0,
LCM_DBI_TE_MODE_VSYNC_ONLY = 1,
LCM_DBI_TE_MODE_VSYNC_OR_HSYNC = 2,
} LCM_DBI_TE_MODE;
typedef enum
{
LCM_DBI_TE_VS_WIDTH_CNT_DIV_8 = 0,
LCM_DBI_TE_VS_WIDTH_CNT_DIV_16 = 1,
LCM_DBI_TE_VS_WIDTH_CNT_DIV_32 = 2,
LCM_DBI_TE_VS_WIDTH_CNT_DIV_64 = 3,
} LCM_DBI_TE_VS_WIDTH_CNT_DIV;
/* DPI related enumerations */
typedef enum
{
LCM_DPI_FORMAT_RGB565 = 0,
LCM_DPI_FORMAT_RGB666 = 1,
LCM_DPI_FORMAT_RGB888 = 2
} LCM_DPI_FORMAT;
typedef enum
{
LCM_SERIAL_CLOCK_FREQ_104M = 0,
LCM_SERIAL_CLOCK_FREQ_26M,
LCM_SERIAL_CLOCK_FREQ_52M
} LCM_SERIAL_CLOCK_FREQ;
typedef enum
{
LCM_SERIAL_CLOCK_DIV_2 = 0,
LCM_SERIAL_CLOCK_DIV_4 = 1,
LCM_SERIAL_CLOCK_DIV_8 = 2,
LCM_SERIAL_CLOCK_DIV_16 = 3,
} LCM_SERIAL_CLOCK_DIV;
/* DSI related enumerations */
typedef enum
{
CMD_MODE = 0,
SYNC_PULSE_VDO_MODE = 1,
SYNC_EVENT_VDO_MODE = 2,
BURST_VDO_MODE = 3
} LCM_DSI_MODE_CON;
typedef enum
{
LCM_ONE_LANE = 1,
LCM_TWO_LANE = 2,
LCM_THREE_LANE = 3,
LCM_FOUR_LANE = 4,
} LCM_LANE_NUM;
typedef enum
{
LCM_DSI_FORMAT_RGB565 = 0,
LCM_DSI_FORMAT_RGB666 = 1,
LCM_DSI_FORMAT_RGB888 = 2
} LCM_DSI_FORMAT;
typedef enum
{
LCM_DSI_TRANS_SEQ_MSB_FIRST = 0,
LCM_DSI_TRANS_SEQ_LSB_FIRST = 1
} LCM_DSI_TRANS_SEQ;
typedef enum
{
LCM_DSI_PADDING_ON_LSB = 0,
LCM_DSI_PADDING_ON_MSB = 1
} LCM_DSI_PADDING;
typedef enum
{
LCM_PACKED_PS_16BIT_RGB565=0,
LCM_LOOSELY_PS_18BIT_RGB666=1,
LCM_PACKED_PS_24BIT_RGB888=2,
LCM_PACKED_PS_18BIT_RGB666=3
} LCM_PS_TYPE;
typedef enum
{
LCM_DSI_6589_PLL_CLOCK_NULL = 0,
LCM_DSI_6589_PLL_CLOCK_201_5 = 1,
LCM_DSI_6589_PLL_CLOCK_208 = 2,
LCM_DSI_6589_PLL_CLOCK_214_5 = 3,
LCM_DSI_6589_PLL_CLOCK_221 = 4,
LCM_DSI_6589_PLL_CLOCK_227_5 = 5,
LCM_DSI_6589_PLL_CLOCK_234 = 6,
LCM_DSI_6589_PLL_CLOCK_240_5 = 7,
LCM_DSI_6589_PLL_CLOCK_247 = 8,
LCM_DSI_6589_PLL_CLOCK_253_5 = 9,
LCM_DSI_6589_PLL_CLOCK_260 = 10,
LCM_DSI_6589_PLL_CLOCK_266_5 = 11,
LCM_DSI_6589_PLL_CLOCK_273 = 12,
LCM_DSI_6589_PLL_CLOCK_279_5 = 13,
LCM_DSI_6589_PLL_CLOCK_286 = 14,
LCM_DSI_6589_PLL_CLOCK_292_5 = 15,
LCM_DSI_6589_PLL_CLOCK_299 = 16,
LCM_DSI_6589_PLL_CLOCK_305_5 = 17,
LCM_DSI_6589_PLL_CLOCK_312 = 18,
LCM_DSI_6589_PLL_CLOCK_318_5 = 19,
LCM_DSI_6589_PLL_CLOCK_325 = 20,
LCM_DSI_6589_PLL_CLOCK_331_5 = 21,
LCM_DSI_6589_PLL_CLOCK_338 = 22,
LCM_DSI_6589_PLL_CLOCK_344_5 = 23,
LCM_DSI_6589_PLL_CLOCK_351 = 24,
LCM_DSI_6589_PLL_CLOCK_357_5 = 25,
LCM_DSI_6589_PLL_CLOCK_364 = 26,
LCM_DSI_6589_PLL_CLOCK_370_5 = 27,
LCM_DSI_6589_PLL_CLOCK_377 = 28,
LCM_DSI_6589_PLL_CLOCK_383_5 = 29,
LCM_DSI_6589_PLL_CLOCK_390 = 30,
LCM_DSI_6589_PLL_CLOCK_396_5 = 31,
LCM_DSI_6589_PLL_CLOCK_403 = 32,
LCM_DSI_6589_PLL_CLOCK_409_5 = 33,
LCM_DSI_6589_PLL_CLOCK_416 = 34,
LCM_DSI_6589_PLL_CLOCK_422_5 = 35,
LCM_DSI_6589_PLL_CLOCK_429 = 36,
LCM_DSI_6589_PLL_CLOCK_435_5 = 37,
LCM_DSI_6589_PLL_CLOCK_442 = 38,
LCM_DSI_6589_PLL_CLOCK_448_5 = 39,
LCM_DSI_6589_PLL_CLOCK_455 = 40,
LCM_DSI_6589_PLL_CLOCK_461_5 = 41,
LCM_DSI_6589_PLL_CLOCK_468 = 42,
LCM_DSI_6589_PLL_CLOCK_474_5 = 43,
LCM_DSI_6589_PLL_CLOCK_481 = 44,
LCM_DSI_6589_PLL_CLOCK_487_5 = 45,
LCM_DSI_6589_PLL_CLOCK_494 = 46,
LCM_DSI_6589_PLL_CLOCK_500_5 = 47,
LCM_DSI_6589_PLL_CLOCK_507 = 48,
LCM_DSI_6589_PLL_CLOCK_513_5 = 49,
LCM_DSI_6589_PLL_CLOCK_520 = 50,
} LCM_DSI_PLL_CLOCK;
// ---------------------------------------------------------------------------
typedef struct
{
LCM_COLOR_ORDER color_order;
LCM_DBI_TRANS_SEQ trans_seq;
LCM_DBI_PADDING padding;
LCM_DBI_FORMAT format;
LCM_DBI_DATA_WIDTH width;
} LCM_DBI_DATA_FORMAT;
typedef struct
{
LCM_POLARITY cs_polarity;
LCM_POLARITY clk_polarity;
LCM_CLOCK_PHASE clk_phase;
unsigned int is_non_dbi_mode;
LCM_SERIAL_CLOCK_FREQ clock_base;
LCM_SERIAL_CLOCK_DIV clock_div;
////////////////////////////////////MT6575 added params, and if lcm driver is for 6575, only care these below params
unsigned int css;
unsigned int csh;
unsigned int rd_1st;
unsigned int rd_2nd;
unsigned int wr_1st;
unsigned int wr_2nd;
unsigned int sif_3wire;
unsigned int sif_sdi;
LCM_POLARITY sif_1st_pol;
LCM_POLARITY sif_sck_def;
unsigned int sif_div2;
unsigned int sif_hw_cs;
////////////////////////////////////
} LCM_DBI_SERIAL_PARAMS;
typedef struct
{
/* timing parameters */
unsigned int write_setup;
unsigned int write_hold;
unsigned int write_wait;
unsigned int read_setup;
unsigned int read_hold;
unsigned int read_latency;
unsigned int wait_period;
/*only for 6575*/
unsigned int cs_high_width;
} LCM_DBI_PARALLEL_PARAMS;
typedef struct
{
LCM_COLOR_ORDER color_order;
LCM_DSI_TRANS_SEQ trans_seq;
LCM_DSI_PADDING padding;
LCM_DSI_FORMAT format;
} LCM_DSI_DATA_FORMAT;
// ---------------------------------------------------------------------------
typedef struct
{
/* common parameters for serial & parallel interface */
unsigned int port;
LCM_DBI_CLOCK_FREQ clock_freq;
LCM_DBI_DATA_WIDTH data_width;
LCM_DBI_DATA_FORMAT data_format;
LCM_DBI_CPU_WRITE_BITS cpu_write_bits;
LCM_DRIVING_CURRENT io_driving_current;
LCM_DRIVING_CURRENT msb_io_driving_current;
/* tearing control */
LCM_DBI_TE_MODE te_mode;
LCM_POLARITY te_edge_polarity;
unsigned int te_hs_delay_cnt;
unsigned int te_vs_width_cnt;
LCM_DBI_TE_VS_WIDTH_CNT_DIV te_vs_width_cnt_div;
/* particular parameters for serial & parallel interface */
LCM_DBI_SERIAL_PARAMS serial;
LCM_DBI_PARALLEL_PARAMS parallel;
} LCM_DBI_PARAMS;
typedef struct
{
/*
Pixel Clock Frequency = 26MHz * mipi_pll_clk_div1
/ (mipi_pll_clk_ref + 1)
/ (2 * mipi_pll_clk_div2)
/ dpi_clk_div
*/
unsigned int mipi_pll_clk_ref; // 0..1
unsigned int mipi_pll_clk_div1; // 0..63
unsigned int mipi_pll_clk_div2; // 0..15
unsigned int mipi_pll_clk_fbk_div; //PCLK=> 8: 26MHz, 10: 35MHz, 12: 40MHz
unsigned int dpi_clk_div; // 2..32
unsigned int dpi_clk_duty; // (dpi_clk_div - 1) .. 31
unsigned int PLL_CLOCK;
unsigned int dpi_clock;
unsigned int ssc_disable;
unsigned int ssc_range;
unsigned int width;
unsigned int height;
unsigned int bg_width;
unsigned int bg_height;
/* polarity parameters */
LCM_POLARITY clk_pol;
LCM_POLARITY de_pol;
LCM_POLARITY vsync_pol;
LCM_POLARITY hsync_pol;
/* timing parameters */
unsigned int hsync_pulse_width;
unsigned int hsync_back_porch;
unsigned int hsync_front_porch;
unsigned int vsync_pulse_width;
unsigned int vsync_back_porch;
unsigned int vsync_front_porch;
/* output format parameters */
LCM_DPI_FORMAT format;
LCM_COLOR_ORDER rgb_order;
unsigned int is_serial_output;
unsigned int i2x_en;
unsigned int i2x_edge;
unsigned int embsync;
unsigned int lvds_tx_en;
/* intermediate buffers parameters */
unsigned int intermediat_buffer_num; // 2..3
/* iopad parameters */
LCM_DRIVING_CURRENT io_driving_current;
LCM_DRIVING_CURRENT lsb_io_driving_current;
} LCM_DPI_PARAMS;
// ---------------------------------------------------------------------------
typedef struct
{
LCM_DSI_MODE_CON mode;
unsigned int DSI_WMEM_CONTI;
unsigned int DSI_RMEM_CONTI;
unsigned int VC_NUM;
LCM_LANE_NUM LANE_NUM;
LCM_DSI_DATA_FORMAT data_format;
/* intermediate buffers parameters */
unsigned int intermediat_buffer_num; // 2..3
LCM_PS_TYPE PS;
unsigned int word_count;
unsigned int packet_size;
unsigned int vertical_sync_active;
unsigned int vertical_backporch;
unsigned int vertical_frontporch;
unsigned int vertical_active_line;
unsigned int horizontal_sync_active;
unsigned int horizontal_backporch;
unsigned int horizontal_frontporch;
unsigned int horizontal_blanking_pixel;
unsigned int horizontal_active_pixel;
unsigned int horizontal_bllp;
unsigned int line_byte;
unsigned int horizontal_sync_active_byte;
unsigned int horizontal_backporch_byte;
unsigned int horizontal_frontporch_byte;
unsigned int rgb_byte;
unsigned int horizontal_sync_active_word_count;
unsigned int horizontal_backporch_word_count;
unsigned int horizontal_frontporch_word_count;
unsigned char HS_TRAIL;
unsigned char HS_ZERO;
unsigned char HS_PRPR;
unsigned char LPX;
unsigned char TA_SACK;
unsigned char TA_GET;
unsigned char TA_SURE;
unsigned char TA_GO;
unsigned char CLK_TRAIL;
unsigned char CLK_ZERO;
unsigned char LPX_WAIT;
unsigned char CONT_DET;
unsigned char CLK_HS_PRPR;
unsigned char CLK_HS_POST;
unsigned char DA_HS_EXIT;
unsigned char CLK_HS_EXIT;
unsigned int pll_select;
unsigned int pll_div1;
unsigned int pll_div2;
unsigned int fbk_div;
unsigned int fbk_sel;
unsigned int rg_bir;
unsigned int rg_bic;
unsigned int rg_bp;
unsigned int PLL_CLOCK;
unsigned int dsi_clock;
unsigned int ssc_disable;
unsigned int ssc_range;
unsigned int compatibility_for_nvk;
unsigned int cont_clock;
unsigned int ufoe_enable;
unsigned int lcm_int_te_monitor;
unsigned int lcm_int_te_period;
unsigned int lcm_ext_te_monitor;
unsigned int lcm_ext_te_enable;
unsigned int noncont_clock;
unsigned int noncont_clock_period;
} LCM_DSI_PARAMS;
// ---------------------------------------------------------------------------
typedef struct
{
LCM_TYPE type;
LCM_CTRL ctrl; //! how to control LCM registers
LCM_INTERFACE_ID lcm_if;
LCM_INTERFACE_ID lcm_cmd_if;
/* common parameters */
unsigned int width;
unsigned int height;
unsigned int io_select_mode; //DBI or DPI should select IO mode according to chip spec
/* particular parameters */
LCM_DBI_PARAMS dbi;
LCM_DPI_PARAMS dpi;
LCM_DSI_PARAMS dsi;
unsigned int physical_width;
unsigned int physical_height;
unsigned int od_table_size;
void *od_table;
} LCM_PARAMS;
// ---------------------------------------------------------------------------
#define REGFLAG_ESCAPE_ID (0x00)
#define REGFLAG_DELAY_MS_V3 (0xFF)
typedef struct {
unsigned char id;
unsigned char cmd;
unsigned char count;
unsigned char para_list[128];
} LCM_setting_table_V3;
typedef struct
{
void (*set_reset_pin)(unsigned int value);
void (*set_chip_select)(unsigned int value);
int (*set_gpio_out)(unsigned int gpio, unsigned int value);
void (*udelay)(unsigned int us);
void (*mdelay)(unsigned int ms);
void (*send_cmd)(unsigned int cmd);
void (*send_data)(unsigned int data);
unsigned int (*read_data)(void);
void (*dsi_set_cmdq_V3)(LCM_setting_table_V3 *para_list, unsigned int size, unsigned char force_update);
void (*dsi_set_cmdq_V2)(unsigned cmd, unsigned char count, unsigned char *para_list, unsigned char force_update);
void (*dsi_set_cmdq)(unsigned int *pdata, unsigned int queue_size, unsigned char force_update);
void (*dsi_write_cmd)(unsigned int cmd);
void (*dsi_write_regs)(unsigned int addr, unsigned int *para, unsigned int nums);
unsigned int (*dsi_read_reg)(void);
unsigned int (*dsi_dcs_read_lcm_reg)(unsigned char cmd);
unsigned int (*dsi_dcs_read_lcm_reg_v2)(unsigned char cmd, unsigned char *buffer, unsigned char buffer_size);
void (*wait_transfer_done)(void);
/** FIXME: GPIO mode should not be configured in lcm driver
REMOVE ME after GPIO customization is done
*/
int (*set_gpio_mode)(unsigned int pin, unsigned int mode);
int (*set_gpio_dir)(unsigned int pin, unsigned int dir);
int (*set_gpio_pull_enable)(unsigned int pin, unsigned char pull_en);
} LCM_UTIL_FUNCS;
typedef enum
{
LCM_DRV_IOCTL_ENABLE_CMD_MODE = 0x100,
}LCM_DRV_IOCTL_CMD;
typedef struct
{
const char* name;
void (*set_util_funcs)(const LCM_UTIL_FUNCS *util);
void (*get_params)(LCM_PARAMS *params);
void (*init)(void);
void (*suspend)(void);
void (*resume)(void);
// for power-on sequence refinement
void (*init_power)(void);
void (*suspend_power)(void);
void (*resume_power)(void);
void (*update)(unsigned int x, unsigned int y, unsigned int width, unsigned int height);
unsigned int (*compare_id)(void);
///////////////////////////CABC backlight related function
void (*set_backlight)(unsigned int level);
void (*set_pwm)(unsigned int divider);
unsigned int (*get_pwm)(unsigned int divider);
void (*set_backlight_mode)(unsigned int mode);
///////////////////////////
/////////////ESD_RECOVERY//////////////////////
unsigned int (*esd_check)(void);
unsigned int (*esd_recover)(void);
unsigned int (*check_status)(void);
unsigned int (*ata_check)(unsigned char *buffer);
void (*read_fb)(unsigned char *buffer);
int (*ioctl)(LCM_DRV_IOCTL_CMD cmd, unsigned int data);
/////////////////////////////////////////////////
} LCM_DRIVER;
// ---------------------------------------------------------------------------
// LCM Driver Functions
// ---------------------------------------------------------------------------
const LCM_DRIVER* LCM_GetDriver(void);
unsigned char which_lcd_module_triple(void);
#endif // __LCM_DRV_H__
arch/arm/mach-mt8127/ford/lcm/inc/mt8193_lvds.h
+357
View File
@@ -0,0 +1,357 @@
// LVDSTX(Base Address:+800h/+900h)
// 1.Basic setting
#define LVDS_OUTPUT_CTRL 0x0818
#define RG_LVDSRX_FIFO_EN 0x80000000 //[31] lvdsrx fifo enable
#define RG_DPMODE 0x00000008 //[3] Reserved for ASFIFO test
#define RG_SYNC_TRIG_MODE 0x00000004 //[2] lvds 7-> trig vsync mode enable
#define RG_OUT_FIFO_EN 0x00000002 //[1] lvds output fifo enable
#define RG_LVDS_E 0x00000001 //[0] lvds 7bit-4bit fifo enable
#define LVDS_CLK_CTRL 0x0820
#define RG_TEST_CK_SEL2 0x00000400 //[10] 0->lvds ifclk, 1->scan clock
#define RG_TEST_CK_SEL1 0x00000200 //[9] 0->lvds ctsclk, 1->scan clock
#define RG_TEST_CK_SEL0 0x00000100 //[8] 0->lvds pclk, 1->scan clock
#define RG_TEST_CK_EN 0x00000004 //[2] lvdstx test pattern clock enable
#define RG_RX_CK_EN 0x00000002 //[1] lvdsrx clock enable
#define RG_TX_CK_EN 0x00000001 //[0] lvdstx clock enable
#define LVDS_CLK_RESET 0x082c
#define RG_CTSCLK_RESET_B 0x00000002 //[1] contraol ctsclk_reset_b
#define RG_PCLK_RESET_B 0x00000001 //[0] control pclk_reset_b
typedef enum
{
LCD_DATA_FORMAT_VESA8BIT = 0,
LCD_DATA_FORMAT_VESA6BIT = 1,
LCD_DATA_FORMAT_DISM8BIT = 2
} LCD_DATA_FMT;
// 2.VESA Standard 8Bit/6Bit encoder
#define LVDS_FMT_CTRL 0x0800
#define RG_8BIT_FORMAT 0x00000000 //[6:4] Data format select 8-bit mode, 000->8bit mode
#define RG_6BIT_FORMAT 0x00000010 //[6:4] Data format select 8-bit mode, 001->6bit mode
#define RG_DE_INV 0x00000004 //[2] Input DE invert
#define RG_VSYNC_INV 0x00000002 //[1] Input VSYNC invert
#define RG_HSYNC_INV 0x00000001 //[0] Input HSYNC invert
// 3.R_SEL/G_SEL/B_SEL should be set to the same value
#define LVDS_R_SEL 0x080c
#define RG_R_SEL_VESA 0x00000000 //VESA Standard
#define RG_R_SEL_DISM 0x00492492 //DISM Standard
#define LVDS_G_SEL 0x0810
#define RG_G_SEL_VESA 0x00000000 //VESA Standard
#define RG_G_SEL_DISM 0x00492492 //DISM Standard
#define LVDS_B_SEL 0x0814
#define RG_B_SEL_VESA 0x00000000 //VESA Standard
#define RG_B_SEL_DISM 0x00492492 //DISM Standard
// 4.Build-in test pattern
#define LVDS_RG_HV_TOTAL 0x0908
#define LVDS_PTGEN_V_TOTAL 0x027b0000 //[27:16] V total From register for test ptgen
#define LVDS_PTGEN_H_TOTAL 0x00000540 //[12:0] H total From register for test ptgen
#define LVDS_RG_HV_WIDTH 0x090c
#define LVDS_PTGEN_V_WIDTH 0x00050000 //[27:16] V width From register for test ptgen
#define LVDS_PTGEN_H_WIDTH 0x00000080 //[12:0] H width From register for test ptgen
#define LVDS_RG_HV_START 0x0910
#define LVDS_PTGEN_V_START 0x00150000 //[27:16] V start From register for test ptgen
#define LVDS_PTGEN_H_START 0x00000118 //[12:0] H start From register for test ptgen
#define LVDS_RG_HV_ACTIVE 0x0914
#define LVDS_PTGEN_V_ACTIVE 0x02580000 //[27:16] V active From register for test ptgen
#define LVDS_PTGEN_H_ACTIVE 0x00000400 //[12:0] H active From register for test ptgen
#define LVDS_RG_PTGEN_CTRL 0x0918
#define LVDS_COLOR_BAR_TH 0x04000000 //[27:16] Threshold of de_v_count for test enable
#define LVDS_PTGEN_TYPE 0x00000200 //[15:8] [1:0] 10:generate configurable color bar
#define LVDS_TST_PAT_EN 0x00000001 //[0] Test Patgen Enable
#define LVDS_RG_PTGEN_BD 0x091c
#define LVDS_PTGEN_BD_B 0x00200000 //[23:16] Background B From register for test ptgen
#define LVDS_PTGEN_BD_G 0x00002000 //[15:8] Background G From register for test ptgen
#define LVDS_PTGEN_BD_R 0x000000ff //[7:0] Background R From register for test ptgen
#define LVDS_RG_PTGEN_DATA 0x0920
#define LVDS_PTGEN_B 0x00ff0000 //[23:16] B From register for test ptgen
#define LVDS_PTGEN_G 0x00002000 //[15:8] G From register for test ptgen
#define LVDS_PTGEN_R 0x00000020 //[7:0] R From register for test ptgen
// 5.CRC check for digital function
#define LVDS_CRC_CTRL 0x0904
#define RG_CRC_CLR 0x00000002 //[1] lvdstx_crc crc check clear control
#define RG_CRC_START 0x00000001 //[0] lvdstx_crc crc check start control
#define LVDS_TX_CRC_STATUS 0x0934
// 6.LVDS analog test
#define LVDS_RG_TST_CH 0x0830
#define RG_LVDS_CH2 0x00a00000 //[23:20] Channel 2 From register for ANA test
#define RG_LVDS_CH1 0x00002800 //[13:10] Channel 1 From register for ANA test
#define RG_LVDS_CH0 0x0000000a //[3:0] Channel 0 From register for ANA test
#define LVDS_RG_TST_CLK 0x0834
#define RG_LVDS_PAT_EN 0x80000000 //[31] Source From register for Analog test enable
#define RG_LVDS_CLK 0x00002800 //[13:10] Clcok channel From register for ANA test
#define RG_LVDS_CH3 0x0000000a //[3:0] Channel 3 From register for ANA test
// 7.Lvdstx_fmt output control
#define LVDS_RG_SRC 0x0804
#define RG_B 0x00000000 //[31:24] Register source for B
#define RG_G 0x00000000 //[23:16] Register source for G
#define RG_R 0x00000000 //[15:8] Register source for R
#define RG_B_SEL 0x00000000 //[5:4] 00->B, 01->R, 10->G, 11->rg_b
#define RG_G_SEL 0x00000000 //[3:2] 00->G, 01->B, 10->R, 11->rg_g
#define RG_R_SEL 0x00000000 //[1:0] 00->R, 01->G, 10->B, 11->rg_r
#define LVDS_RG_CTRL 0x0808
#define RG_DE 0x00000000 //[8] Register source for DE
#define RG_VSYNC 0x00000000 //[7] Register source for VSYNC
#define RG_HSYNC 0x00000000 //[6] Register source for HSYNC
#define RG_DE_SEL 0x00000000 //[5:4] 00->de, 01->hsync, 10->vsync, 11->rg_de
#define RG_VSYNC_SEL 0x00000000 //[3:2] 00->vsync, 01->de, 10->hsync, 11->rg_vsync
#define RG_HSYNC_SEL 0x00000000 //[1:0] 00->hsync, 01->vsync, 10->de, 11->rg_hsync
// 8.Channel swap and bit invert
#define LVDS_CH_SWAP 0x081c
#define RG_SWAP_SEL 0x80000000 //[31] lvds_pa*_tmds_[6:0] Swap
#define RG_TOP_PN 0x00000000 //[28:24] Channel P/N Swap
#define RG_ML_SWAP 0x00000000 //[20:16] Channel MSB/LSB Swap
#define RG_CLK_SEL 0x00000000 //[14:12] Clock channel source select
#define RG_CH3_SEL 0x00000000 //[11:9] Channel 3 Source select
#define RG_CH2_SEL 0x00000000 //[8:6] Channel 2 Source select
#define RG_CH1_SEL 0x00000000 //[5:3] Channel 1 Source select
#define RG_CH0_SEL 0x00000000 //[2:0] Channel 0 Source select
// DGI0 (Base Address:+400h/+500h)
// 1.Basic setting
#define DGI0_DEC_CTRL 0x0400
#define FIFO_WRITE_EN 0x00008000 //[15] fifo write enable
#define RESET_COUNTER 0x08000000 //[27] reset the counter for timing generate
#define CLEAR_COUNTER 0x00000000
#define DGI0_FIFO_CTRL 0x0404
#define SW_RST 0x00080000 //[19] soft reset
#define FIFO_RESET_ON 0x00020000 //[17] fifo reset or not
#define RD_START 0x00000040 //[6:0]
#define DGI0_DATA_OUT_CTRL 0x0408
#define DATA_OUT_SWAP 0x04000000 //[26]rise fifo data and fall fifo swap bit
#define TTL_TIM_SWAP 0x00003000 //[14:12] ttl out timing swap HSYNC ->DE
#define TTL_TIM_SWAP2 0x00005000 //[14:12] ttl out timing swap VSYNC ->DE
#define DGI0_DITHER_CTRL0 0x0410
#define FRC_EN 0x10000000 //[28] frc dither enable
#define FCNT_DIF_EN 0x00000800 //[11] fcnt diffuse enable
#define SYNC_SEL 0x00000200 //[9] 0->internal sync generation by input DE, 1->input sync
#define OUT_FMT 0x00000010 //[5:4] 00->4bit, 01->6bit, 10->8bit, 11->10bit
#define DGI0_DITHER_CTRL1 0x0414
#define DGI0_DITHER_CTRL2 0x0418
#define DGI0_TG_CTRL00 0x041c
#define PRGS_OUT 0x00104000 //[20] progressive out
#define DGI0_TG_CTRL01 0x0420
#define RG_VSYNC_FORWARD 0x80000000 //[31] verical delay forward or back
#define RG_VSYNC_DELAY 0x00020000 //[28:16] vertical delay
#define RG_HSYNC_DELAY 0x000003a8 //[12:0] horizontal delay
#define DGI0_TG_CTRL02 0x0424
#define VSYNC_TOTAL 0x020d0000 //[27:16] vertical total
#define HSYNC_TOTAL 0x000003aa //[12:0] horizontal total
#define DGI0_TG_CTRL03 0x0428
#define VSYNC_WIDTH 0x00060000 //[24:16] vsync width
#define HSYNC_WIDTH 0x0000003e //[11:0] hsync width
#define DGI0_TG_CTRL04 0x042c
#define H_ACT2_EN 0x00000400 //[10] horizontal active 2 enable
#define V_ACT2_EN 0x00000200 //[9] vertical active 2 enable
#define HD_ON 0x00000100 //[8] HD on
#define VSYNC_POL 0x00000040 //[6] vsync polarity
#define HSYNC_POL 0x00000020 //[5] hsync polarity
#define DE_POL 0x00000010 //[4] de polarity
#define DGI0_TG_CTRL05 0x0430
#define X_ACTIVE_START 0x007a0000 //[28:16] horizontal start point
#define X_ACTIVE_END 0x00000399 //[12:0] horizontal end point
#define DGI0_TG_CTRL06 0x0434
#define Y_ACTIVE_OSTART 0x00240000 //[27:16] odd vertical start point
#define Y_ACTIVE_OEND 0x00000203 //[11:0] odd vertical end point
#define DGI0_TG_CTRL07 0x0438
#define Y_ACTIVE_ESTART 0x00240000 //[27:16] even vertical start point
#define Y_ACTIVE_EEND 0x00000203 //[11:0] even vertical end point
#define DGI0_TG_CTRL08 0x043c
#define X_ACTIVE_START_1 0x007a0000 //[28:16] horizontal start point 1
#define X_ACTIVE_END_1 0x00000399 //[12:0] horizontal end point 1
#define DGI0_TG_CTRL09 0x0440
#define Y_ACTIVE_OSTART_1 0x00240000 //[27:16] odd vertical start point 1
#define Y_ACTIVE_OEND_1 0x00000203 //[11:0] odd vertical end point 1
#define DGI0_TG_CTRL10 0x0444
#define Y_ACTIVE_ESTART_1 0x00240000 //[27:16] even vertical start point 1
#define Y_ACTIVE_EEND_1 0x00000203 //[11:0] even vertical end point 1
#define DGI0_ANAIF_CTRL2 0x0448
#define HDMIPLL_REG_CLK_SEL 0x00000000 //[31] hdmipll reference clock select bit, 0->dgi1_ref_clk, 1->dgi0_ref_clk
#define DGI1_DEL_D2_D4_SEL 0x00000000 //[17] dgi1 reference clock devide 2 or devide 4 select, 0->devide 2, 1->devide 4
#define DGI1_DEL_D1_SEL 0x00000000 //[16] dgi1 reference clock devide 1 select, 0->devide 1, 1->select the d2_d4 clock
#define DGI0_DEL_D2_D4_SEL 0x00000000 //[1] dgi0 reference clock devide 2 or devide 4 select, 0->devide 2, 1->devide 4
#define DGI0_DEL_D1_SEL 0x00000000 //[0] dgi0 reference clock devide 1 select, 0->devide 1, 1->select the d2_d4 clock
#define DGI0_ANAIF_CTRL0 0x044c
#define DGI0_CLK_DELAY_SEL1 0x0000000 //[29:24] dgi0 clock delay chain select 1
#define DGI0_CLK_DELAY_SEL0 0x0000000 //[21:16] dgi0 clock delay chain select 0
#define DGI0_CK_INV_PRE_CTRL 0x0000000 //[1] dgi0 pad clock invert
#define DGI0_PAD_CLK_ENABLE 0x0000001 //[0] dgi0 pad clock enable
#define DGI0_PAD_CLK_DISABLE 0x0000000 //[0] dgi0 pad clock disable
#define DGI0_ANAIF_CTRL1 0x0450
#define DGI1_PAD_CLK_INV_EN 0x0000000 //[31] invter clock
#define DGI1_CLK_DELAY_SEL1 0x0000000 //[29:24] dgi1 clock delay chain select 1
#define DGI1_CLK_DELAY_SEL0 0x0000000 //[21:16] dgi1 clock delay chain select 0
#define DATA_IN_TV_MODE 0x0000000 //[9] data in TV mode
#define DATA_IN_BIT_INV 0x0000000 //[8] data in bit inv
#define ANAIF_DGI1_CLK_SEL 0x0000000 //[6] anaif dgi1 clock select from dgi0 clock or dgi1 clock
#define CLK_SEL_TV_MODE 0x0000000 //[4] clock in TV mode
#define CLK_MODE_SEL 0x0000000 //[3] clock mode select
#define NWEB_CLK_EN 0x0000000 //[2] nweb clock enable
#define DGI1_PAD_CLK_EN 0x0000000 //[1] dgi1 pad clk enable
#define TV_MODE_CLK_EN 0x0000000 //[0] TV mode clock enable
#define DGI0_TTL_ANAIF_CTRL 0x0454
#define TTL_CLK_TEST_MODE 0x00000000 //[31] ttl clock test mode, 0->lvds display clock, 1->dgi0 anaif clock
#define TTL_CLK_DELAY_SEL1 0x00000000 //[21:16] ttl clock delay chain select 1
#define TTL_CLK_DELAY_SEL0 0x00000000 //[13:8] ttl clock delay chain select 0
#define TTL_CLK_INV_ENABLE 0x00000001 //[0] ttl clock invert enable
#define DGI0_TTL_ANAIF_CTRL1 0x0458
#define PAD_TTL_EN_PP 0x00000002 //[1] enable ttl out preplace, set to 1
#define PAD_TTL_EN_FUN_SEL 0x00000001 //[0] TTL Pinmux, 1->function 2, 0->function 1
#define DGI0_CLK_RST_CTRL 0x045c
#define DGI0_TEST_MODE 0x80000000 //[31] dgi0 clk_out test mode
#define CLK_OUT_TO_IN_INV 0x00000000 //[5] clk_in_inv use clk_out when pat_gen
#define CLK_OUT_TO_IN 0x00000000 //[4] clk_in use clk_out when pat_gen
#define CLK_PAT_GEN_EN 0x00000008 //[3] pat_gen clock enable
#define DGI0_CLK_OUT_ENABLE 0x00000004 //[2] dgi0 clk_out enable
#define DGI0_CLK_IN_INV_ENABLE 0x00000002 //[1] dgi0 clk_in_inv enable
#define DGI0_CLK_IN_ENABLE 0x00000001 //[0] dgi0 clk_in enable
#define DGI0_CLK_OUT_DISABLE 0x00000000 //[2] dgi0 clk_out disable
#define DGI0_PAT_GEN_CTRL0 0x0500
#define RG_PTGEN_V_TOTAL 0x027b0000 //[27:16] V total From register for test ptgen
#define RG_PTGEN_H_TOTAL 0x00000540 //[12:0] H total From register for test ptgen
#define DGI0_PAT_GEN_CTRL1 0x0504
#define RG_PTGEN_V_WIDTH 0x00050000 //[27:16] V width From register for test ptgen
#define RG_PTGEN_H_WIDTH 0x00000080 //[12:0] H width From register for test ptgen
#define DGI0_PAT_GEN_CTRL2 0x0508
#define RG_PTGEN_V_START 0x00150000 //[27:16] V start From register for test ptgen
#define RG_PTGEN_H_START 0x00000118 //[12:0] H start From register for test ptgen
#define DGI0_PAT_GEN_CTRL3 0x050c
#define RG_PTGEN_V_ACTIVE 0x02580000 //[27:16] V active From register for test ptgen
#define RG_PTGEN_H_ACTIVE 0x00000400 //[12:0] H active From register for test ptgen
#define DGI0_PAT_GEN_CTRL4 0x0510
#define RG_COLOR_BAR_TH 0x04000000 //[27:16] Threshold of de_v_count for test enable
#define RG_PTGEN_TYPE 0x00000200 //[15:8] [1:0]=10:generate configurable color bar
#define PAT_GEN_RST 0x00000004 //[2] pat_gen reset
#define PAT_IN 0x00000002 //[1] data in use pattern gen data
#define RG_TST_PAT_EN 0x00000001 //[0] Test Patgen Enable
#define DGI0_PAT_GEN_CTRL5 0x0514
#define RG_PTGEN_BD_B 0x00ff0000 //[23:16] Background B From register for test ptgen
#define RG_PTGEN_BD_G 0x00008800 //[15:8] Background G From register for test ptgen
#define RG_PTGEN_BD_R 0x00000044 //[7:0] Background R From register for test ptgen
#define DGI0_PAT_GEN_CTRL6 0x0518
#define RG_PTGEN_B 0x00ff0000 //[23:16] B From register for test ptgen
#define RG_PTGEN_G 0x00008800 //[15:8] G From register for test ptgen
#define RG_PTGEN_R 0x00000044 //[7:0] R From register for test ptgen
#define DGI0_CRC_MON_CT 0x051c
#define C_CRC_CLR 0x00000002
#define C_CRC_START 0x00000001
#define DGI0_CRC_OUT 0x0520
#define CRC_RDY 0x10000000
#define CRC_OUT 0x00ffffff
#define DGI0_MON 0x0524
//ckgen setting
#define REG_LVDS_DISP_CKCFG 0x1014
#define REG_LVDS_CTSCLKCFG 0x1018
#define REG_LVDS_PWR_RST_B 0x1108
#define REG_LVDS_PWR_CTRL 0x110c
#define RG_LVDSWRAP_CTRL1 0x1254
#define RG_DCXO_POR_MON_EN 0x00000100 //[8]dcxo_por mon enable
#define RG_PLL1_DIV 0x00000004 //[3:0] rg_pll1_div
#define RG_PLL1_DIV2 0x00000002 //[3:0] rg_pll1_div
#define RG_PLL1_DIV3 0x00000006 //[3:0] rg_pll1_div
#define REG_LVDS_ANACFG0 0x1310
#define RG_LVDS_APD 0xf8000000 //[31:27]
#define RG_LVDS_BIASA_PD 0x02000000 //[25]
#define RG_LVDS_ATERM_EN 0x00800000 //[24:23]00: No source termination; 10: 1k Ohm termination; 01: 100 Ohm termination; 11: 90 Ohm termination;
#define RG_LVDS_APSRC 0x00400000 //[22:20]LVDS A Group P Slew Rate Control; Strongest: 000; Weakest: 111
#define RG_LVDS_ANSRC 0x00070000 //[19:17]LVDS A Group N Slew Rate Control; Strongest: 111; Weakest: 000
#define RG_LVDS_ATVCM 0x0000c000 //[16:14]LVDS A Group Common Mode Voltage Control
#define RG_LVDS_ATVO 0x00002000 //LVDS A Group Output Swing Control
#define REG_LVDS_ANACFG1 0x1314
#define RG_LVDS_AE4 0x80000000 //[31]A Group TTL Output Enable 4ma strength control.
#define RG_LVDS_AE8 0x40000000 //[30]A Group TTL Output Enable 8ma strength control.
#define RG_LVDS_ASR 0x20000000 //[29]A Group TTL Output Slew Rate control
#define RG_LVDS_ASMTEN 0x10000000 //[28]A Group TTL Input Smitch Trigger Enable
#define RG_LVDS_AMINI_SEL_CK0 0x00000000 //[1] A Group Mini-LVDS ck channel enable
#define REG_LVDS_ANACFG2 0x1318
#define RG_VPLL_BC 0x30000000 //[31:27]Integral path cap value
#define RG_VPLL_BIC 0x02000000 //[26:24]Integral path charge pump current
#define RG_VPLL_BIR 0x00200000 //[23:20]Proportional path charge pump current
#define RG_VPLL_BP 0x00010000 //[19:16]Power down for VOPLL Bias
#define RG_VPLL_BG_PD 0x00008000 //[15]Power down for Bandgap
#define RG_VPLL_BR 0x00005000 //[14:12]Proportional path res value
#define RG_VPLL_BIAS_PD 0x00000800 //[11]Power down for VOPLL Bias
#define REG_LVDS_ANACFG3 0x131c
#define RG_VPLL_DIV 0x00040000 //[21:17]Divider setting
#define RG_VPLL_DPIX_CKSEL 0x00001000 //[13:12]VPLL_DPIX_CLK Selection
#define RG_LVDS_DELAY 0x00000080 //[10:8]LVDS_DPIX_CLK Delay setting 70ps / step
#define RG_VPLL_MKVCO 0x00000040 //[7]VCO Range From 160 MHz~ 390 MHz
#define RG_VPLL_POSTDIV_EN 0x00000010 //[4]
#define REG_LVDS_ANACFG4 0x1320
#define RG_VPLL_RST 0x00800000 //[23]
#define RG_T2TTLO_EN 0x00000800 //[11]
#define RG_VPLL_PD 0x00000400 //[10]
#define RG_BYPASS 0x00000200 //[9]mini clock by pass phase interpolater
#define RG_LVDS_BYPASS 0x00000100 //[8]
#define REG_PLL_GPANACFG0 0x134c
#define RG_PLL1_EN 0x80000000 //[31]Power Down 0: Power down 1: Power on
#define RG_PLL1_FBDIV 0x4c000000 //[30:26] Feedback divide ratio (N+1 Divider)
#define RG_PLL1_FBDIV2 0x2c000000 //
#define RG_PLL1_FBDIV3 0x6c000000 //
#define RG_PLL1_PREDIV 0x01000000 //[25:24] Pre-divider ratio
#define RG_PLL1_RST_DLY 0x00300000 //[21:20]Reset Time Control,Tin=1/Fref 00: 2^5 * Tin
#define RG_PLL1_LF 0x00000800 //[11]Frequency Band Control
#define RG_PLL1_MONCKEN 0x00000100 //[8]PLL1 clock monitor enable
#define RG_PLL1_VODEN 0x00000080 //[7]CHP OverDrive Enable
#define RG_NFIPLL_EN 0x00000002 //[1]Power Down 0: Power down 1: Power on
arch/arm/mach-mt8127/ford/lcm/inc/sn65dsi83_i2c.h
+29
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@@ -0,0 +1,29 @@
/*****************************************************************************
*
* Filename:
* ---------
* sn65dsi83.h
*
* Project:
* --------
* Android
*
* Description:
* ------------
* sn65dsi83 header file
*
* Author:
* -------
*
****************************************************************************/
#ifndef _sn65dsi83_SW_H_
#define _sn65dsi83_SW_H_
#ifndef BUILD_LK
//---------------------------------------------------------
extern int sn65dsi83_read_byte(kal_uint8 cmd, kal_uint8 *returnData);
extern int sn65dsi83_write_byte(kal_uint8 cmd, kal_uint8 writeData);
#endif
#endif // _fan5405_SW_H_
arch/arm/mach-mt8127/ford/lcm/mt65xx_lcm_list.c
+964
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@@ -0,0 +1,964 @@
#include <lcm_drv.h>
#ifdef BUILD_LK
#include <platform/disp_drv_platform.h>
#else
#include <linux/delay.h>
#include <mach/mt_gpio.h>
#endif
#include <cust_gpio_usage.h>
//used to identify float ID PIN status
#define LCD_HW_ID_STATUS_LOW 0
#define LCD_HW_ID_STATUS_HIGH 1
#define LCD_HW_ID_STATUS_FLOAT 0x02
#define LCD_HW_ID_STATUS_ERROR 0x03
#ifdef BUILD_LK
#define LCD_DEBUG(fmt) dprintf(CRITICAL,fmt)
#else
#define LCD_DEBUG(fmt) printk(fmt)
#endif
extern LCM_DRIVER otm1282a_hd720_dsi_vdo_lcm_drv;
extern LCM_DRIVER r63319_wqhd_dsi_vdo_truly_lcm_drv;
extern LCM_DRIVER nt35598_wqhd_dsi_vdo_truly_lcm_drv;
extern LCM_DRIVER lp079x01_lcm_drv;
extern LCM_DRIVER hx8369_lcm_drv;
extern LCM_DRIVER hx8369_6575_lcm_drv;
extern LCM_DRIVER hx8363_6575_dsi_lcm_drv;
extern LCM_DRIVER hx8363_6575_dsi_hvga_lcm_drv;
extern LCM_DRIVER hx8363_6575_dsi_qvga_lcm_drv;
extern LCM_DRIVER hx8363b_wvga_dsi_cmd_drv;
extern LCM_DRIVER bm8578_lcm_drv;
extern LCM_DRIVER nt35582_mcu_lcm_drv;
extern LCM_DRIVER nt35582_mcu_6575_lcm_drv;
extern LCM_DRIVER nt35582_rgb_6575_lcm_drv;
extern LCM_DRIVER hx8357b_lcm_drv;
extern LCM_DRIVER hx8357c_hvga_dsi_cmd_drv;
extern LCM_DRIVER hx8369_dsi_lcm_drv;
extern LCM_DRIVER hx8369_dsi_6575_lcm_drv;
extern LCM_DRIVER hx8369_dsi_6575_hvga_lcm_drv;
extern LCM_DRIVER hx8369_dsi_6575_qvga_lcm_drv;
extern LCM_DRIVER hx8369_dsi_vdo_lcm_drv;
extern LCM_DRIVER hx8369b_dsi_vdo_lcm_drv;
extern LCM_DRIVER hx8369b_wvga_dsi_vdo_drv;
extern LCM_DRIVER hx8389b_qhd_dsi_vdo_drv;
extern LCM_DRIVER hx8369_hvga_lcm_drv;
extern LCM_DRIVER ili9481_lcm_drv;
extern LCM_DRIVER nt35582_lcm_drv;
extern LCM_DRIVER s6d0170_lcm_drv;
extern LCM_DRIVER spfd5461a_lcm_drv;
extern LCM_DRIVER ta7601_lcm_drv;
extern LCM_DRIVER tft1p3037_lcm_drv;
extern LCM_DRIVER ha5266_lcm_drv;
extern LCM_DRIVER hsd070idw1_lcm_drv;
extern LCM_DRIVER lg4571_lcm_drv;
extern LCM_DRIVER lg4573b_wvga_dsi_vdo_lh430mv1_drv;
extern LCM_DRIVER lvds_wsvga_lcm_drv;
extern LCM_DRIVER lvds_wsvga_ti_lcm_drv;
extern LCM_DRIVER lvds_wsvga_ti_n_lcm_drv;
extern LCM_DRIVER nt35565_3d_lcm_drv;
extern LCM_DRIVER tm070ddh03_lcm_drv;
extern LCM_DRIVER r61408_lcm_drv;
extern LCM_DRIVER r61408_wvga_dsi_cmd_drv;
extern LCM_DRIVER nt35510_lcm_drv;
extern LCM_DRIVER nt35510_dpi_lcm_drv;
extern LCM_DRIVER nt35510_hvga_lcm_drv;
extern LCM_DRIVER nt35510_qvga_lcm_drv;
extern LCM_DRIVER nt35510_wvga_dsi_cmd_drv;
extern LCM_DRIVER nt35510_6517_lcm_drv;
extern LCM_DRIVER nt35510_dsi_cmd_6572_drv;
extern LCM_DRIVER nt35510_dsi_cmd_6572_hvga_drv;
extern LCM_DRIVER nt35510_dsi_cmd_6572_fwvga_drv;
extern LCM_DRIVER nt35510_dsi_cmd_6572_qvga_drv;
extern LCM_DRIVER nt35510_dsi_vdo_6572_drv;
extern LCM_DRIVER nt35510_dpi_6572_lcm_drv;
extern LCM_DRIVER nt35510_mcu_6572_lcm_drv;
extern LCM_DRIVER nt51012_hd720_dsi_vdo_lcm_drv;
extern LCM_DRIVER r63303_idisplay_lcm_drv;
extern LCM_DRIVER hj080ia_lcm_drv;
extern LCM_DRIVER hj101na02a_lcm_drv;
extern LCM_DRIVER hj101na02a_8135_lcm_drv;
extern LCM_DRIVER hsd070pfw3_lcm_drv;
extern LCM_DRIVER hsd070pfw3_8135_lcm_drv;
extern LCM_DRIVER cm_n070ice_dsi_vdo_lcm_drv;
extern LCM_DRIVER ej101ia_lcm_drv;
extern LCM_DRIVER scf0700m48ggu02_lcm_drv;
extern LCM_DRIVER nt35510_fwvga_lcm_drv;
#if defined(GN_SSD2825_SMD_S6E8AA)
extern LCM_DRIVER gn_ssd2825_smd_s6e8aa;
#endif
extern LCM_DRIVER nt35517_dsi_vdo_lcm_drv;
extern LCM_DRIVER hx8369_dsi_bld_lcm_drv;
extern LCM_DRIVER hx8369_dsi_tm_lcm_drv;
extern LCM_DRIVER otm1280a_hd720_dsi_cmd_drv;
extern LCM_DRIVER otm8018b_dsi_vdo_lcm_drv;
extern LCM_DRIVER otm8018b_dsi_vdo_txd_fwvga_lcm_drv;
extern LCM_DRIVER nt35512_dsi_vdo_lcm_drv;
extern LCM_DRIVER nt35512_wvga_dsi_vdo_boe_drv;
extern LCM_DRIVER hx8369_rgb_6585_fpga_lcm_drv;
extern LCM_DRIVER hx8369_rgb_6572_fpga_lcm_drv;
extern LCM_DRIVER hx8369_mcu_6572_lcm_drv;
extern LCM_DRIVER hx8369a_wvga_dsi_cmd_drv;
extern LCM_DRIVER hx8369a_wvga_dsi_vdo_drv;
extern LCM_DRIVER hx8392a_dsi_cmd_lcm_drv;
extern LCM_DRIVER nt35590_hd720_dsi_vdo_truly_lcm_drv;
extern LCM_DRIVER ssd2075_hd720_dsi_vdo_truly_lcm_drv;
extern LCM_DRIVER nt35590_hd720_dsi_cmd_drv;
extern LCM_DRIVER nt35590_hd720_dsi_cmd_auo_lcm_drv;
extern LCM_DRIVER nt35590_hd720_dsi_cmd_auo_fwvga_lcm_drv;
extern LCM_DRIVER nt35590_hd720_dsi_cmd_auo_wvga_lcm_drv;
extern LCM_DRIVER nt35590_hd720_dsi_cmd_auo_qhd_lcm_drv;
extern LCM_DRIVER nt35590_hd720_dsi_cmd_cmi_lcm_drv;
extern LCM_DRIVER nt35516_qhd_dsi_cmd_ipsboe_lcm_drv;
extern LCM_DRIVER nt35516_qhd_dsi_cmd_ipsboe_wvga_lcm_drv;
extern LCM_DRIVER nt35516_qhd_dsi_cmd_ipsboe_fwvga_lcm_drv;
extern LCM_DRIVER nt35516_qhd_dsi_cmd_ips9k1431_drv;
extern LCM_DRIVER nt35516_qhd_dsi_cmd_tft9k1342_drv;
extern LCM_DRIVER bp070ws1_lcm_drv;
extern LCM_DRIVER bp101wx1_lcm_drv;
extern LCM_DRIVER bp101wx1_n_lcm_drv;
extern LCM_DRIVER nt35516_qhd_rav4_lcm_drv;
extern LCM_DRIVER r63311_fhd_dsi_vdo_sharp_lcm_drv;
extern LCM_DRIVER r81592_hvga_dsi_cmd_drv;
extern LCM_DRIVER rm68190_dsi_vdo_lcm_drv;
extern LCM_DRIVER nt35596_fhd_dsi_vdo_truly_lcm_drv;
extern LCM_DRIVER nt35595_fhd_dsi_vdo_truly_lcm_drv;
extern LCM_DRIVER nt35595_fhd_dsi_cmd_truly_lcm_drv;
extern LCM_DRIVER nt35595_fhd_dsi_cmd_truly_tps65132_lcm_drv;
extern LCM_DRIVER nt35595_fhd_dsi_cmd_truly_tps65132_720p_lcm_drv;
extern LCM_DRIVER nt35596_fhd_dsi_vdo_yassy_lcm_drv;
extern LCM_DRIVER nt35590_hd720_dsi_cmd_truly2_lcm_drv;
extern LCM_DRIVER otm9608_wvga_dsi_cmd_drv;
extern LCM_DRIVER nt35510_dbi_18bit_gionee_lcm_drv;
extern LCM_DRIVER otm8009a_fwvga_dsi_cmd_tianma_lcm_drv;
extern LCM_DRIVER otm8009a_fwvga_dsi_vdo_tianma_lcm_drv;
extern LCM_DRIVER hx8389b_qhd_dsi_vdo_tianma_lcm_drv;
extern LCM_DRIVER cm_otc3108bhv161_dsi_vdo_lcm_drv;
extern LCM_DRIVER auo_b079xat02_dsi_vdo_lcm_drv;
extern LCM_DRIVER hx8389b_qhd_dsi_vdo_tianma055xdhp_lcm_drv;
extern LCM_DRIVER cpt_claa101fp01_dsi_vdo_lcm_drv;
extern LCM_DRIVER h070d_18dm_lcm_drv;
extern LCM_DRIVER hx8394a_hd720_dsi_vdo_tianma_lcm_drv;
extern LCM_DRIVER cpt_clap070wp03xg_sn65dsi83_lcm_drv;
extern LCM_DRIVER nt35520_hd720_tm_lcm_drv;
extern LCM_DRIVER nt35520_hd720_boe_lcm_drv;
extern LCM_DRIVER nt35521_hd720_dsi_vdo_boe_lcm_drv;
extern LCM_DRIVER nt35521_hd720_tm_lcm_drv;
extern LCM_DRIVER r69429_wuxga_dsi_vdo_lcm_drv;
extern LCM_DRIVER r69429_wuxga_dsi_cmd_lcm_drv;
extern LCM_DRIVER rm68210_hd720_dsi_ufoe_cmd_lcm_drv;
extern LCM_DRIVER r63311_fhd_dsi_vedio_lcm_drv;
extern LCM_DRIVER cpt_clap070wp03xg_lvds_lcm_drv;
extern LCM_DRIVER otm8018b_dsi_vdo_lcsh72_lcm_drv;
extern LCM_DRIVER hx8369_dsi_cmd_6571_lcm_drv;
extern LCM_DRIVER hx8369_dsi_vdo_6571_lcm_drv;
extern LCM_DRIVER hx8369_dbi_6571_lcm_drv;
extern LCM_DRIVER hx8369_dpi_6571_lcm_drv;
extern LCM_DRIVER nt35510_dsi_cmd_6571_lcm_drv;
extern LCM_DRIVER nt35510_dsi_cmd_6571_hvga_lcm_drv;
extern LCM_DRIVER nt35510_dsi_cmd_6571_qvga_lcm_drv;
extern LCM_DRIVER nt35510_dsi_vdo_6571_lcm_drv;
extern LCM_DRIVER nt35510_dbi_6571_lcm_drv;
extern LCM_DRIVER nt35510_dpi_6571_lcm_drv;
extern LCM_DRIVER nt35590_dsi_cmd_6571_fwvga_lcm_drv;
extern LCM_DRIVER nt35590_dsi_cmd_6571_qhd_lcm_drv;
extern LCM_DRIVER it6151_edp_dsi_video_sharp_lcm_drv;
extern LCM_DRIVER nt35517_qhd_dsi_vdo_lcm_drv;
extern LCM_DRIVER hx8389b_qhd_dsi_vdo_lgd_lcm_drv;
extern LCM_DRIVER it6151_fhd_edp_dsi_video_auo_lcm_drv;
extern LCM_DRIVER tf070mc_rgb_v18_mt6571_lcm_drv;
extern LCM_DRIVER zs070ih5015b3h6_mt6571_lcm_drv;
extern LCM_DRIVER a080ean01_dsi_vdo_lcm_drv;
LCM_DRIVER* lcm_driver_list[] =
{
#if defined(OTM8018B_DSI_VDO_TXD_FWVGA)
&otm8018b_dsi_vdo_txd_fwvga_lcm_drv,
#endif
#if defined(TF070MC_RGB_V18_MT6571)
&tf070mc_rgb_v18_mt6571_lcm_drv,
#endif
#if defined(ZS070IH5015B3H6_RGB_MT6571)
&zs070ih5015b3h6_mt6571_lcm_drv,
#endif
#if defined(OTM1282A_HD720_DSI_VDO)
&otm1282a_hd720_dsi_vdo_lcm_drv,
#endif
#if defined(R63311_FHD_DSI_VDO)
&r63311_fhd_dsi_vedio_lcm_drv,
#endif
#if defined(NT35517_QHD_DSI_VDO)
&nt35517_dsi_vdo_lcm_drv,
#endif
#if defined(LP079X01)
&lp079x01_lcm_drv,
#endif
#if defined(HX8369)
&hx8369_lcm_drv,
#endif
#if defined(HX8369_6575)
&hx8369_6575_lcm_drv,
#endif
#if defined(BM8578)
&bm8578_lcm_drv,
#endif
#if defined(NT35582_MCU)
&nt35582_mcu_lcm_drv,
#endif
#if defined(NT35582_MCU_6575)
&nt35582_mcu_6575_lcm_drv,
#endif
#if defined(NT35590_HD720_DSI_CMD_TRULY2)
&nt35590_hd720_dsi_cmd_truly2_lcm_drv,
#endif
#if defined(NT35590_HD720_DSI_VDO_TRULY)
&nt35590_hd720_dsi_vdo_truly_lcm_drv,
#endif
#if defined(SSD2075_HD720_DSI_VDO_TRULY)
&ssd2075_hd720_dsi_vdo_truly_lcm_drv,
#endif
#if defined(NT35590_HD720_DSI_CMD)
&nt35590_hd720_dsi_cmd_drv,
#endif
#if defined(NT35590_HD720_DSI_CMD_AUO)
&nt35590_hd720_dsi_cmd_auo_lcm_drv,
#endif
#if defined(NT35590_HD720_DSI_CMD_AUO_WVGA)
&nt35590_hd720_dsi_cmd_auo_wvga_lcm_drv,
#endif
#if defined(NT35590_HD720_DSI_CMD_AUO_QHD)
&nt35590_hd720_dsi_cmd_auo_qhd_lcm_drv,
#endif
#if defined(NT35590_HD720_DSI_CMD_AUO_FWVGA)
&nt35590_hd720_dsi_cmd_auo_fwvga_lcm_drv,
#endif
#if defined(NT35590_HD720_DSI_CMD_CMI)
&nt35590_hd720_dsi_cmd_cmi_lcm_drv,
#endif
#if defined(NT35582_RGB_6575)
&nt35582_rgb_6575_lcm_drv,
#endif
#if defined(NT51012_HD720_DSI_VDO)
&nt51012_hd720_dsi_vdo_lcm_drv,
#endif
#if defined(HX8369_RGB_6585_FPGA)
&hx8369_rgb_6585_fpga_lcm_drv,
#endif
#if defined(HX8369_RGB_6572_FPGA)
&hx8369_rgb_6572_fpga_lcm_drv,
#endif
#if defined(HX8369_MCU_6572)
&hx8369_mcu_6572_lcm_drv,
#endif
#if defined(HX8369A_WVGA_DSI_CMD)
&hx8369a_wvga_dsi_cmd_drv,
#endif
#if defined(HX8369A_WVGA_DSI_VDO)
&hx8369a_wvga_dsi_vdo_drv,
#endif
#if defined(HX8357B)
&hx8357b_lcm_drv,
#endif
#if defined(HX8357C_HVGA_DSI_CMD)
&hx8357c_hvga_dsi_cmd_drv,
#endif
#if defined(R61408)
&r61408_lcm_drv,
#endif
#if defined(R61408_WVGA_DSI_CMD)
&r61408_wvga_dsi_cmd_drv,
#endif
#if defined(HX8369_DSI_VDO)
&hx8369_dsi_vdo_lcm_drv,
#endif
#if defined(HX8369_DSI)
&hx8369_dsi_lcm_drv,
#endif
#if defined(HX8369_6575_DSI)
&hx8369_dsi_6575_lcm_drv,
#endif
#if defined(HX8369_6575_DSI_NFC_ZTE)
&hx8369_dsi_6575_lcm_drv,
#endif
#if defined(HX8369_6575_DSI_HVGA)
&hx8369_dsi_6575_hvga_lcm_drv,
#endif
#if defined(HX8369_6575_DSI_QVGA)
&hx8369_dsi_6575_qvga_lcm_drv,
#endif
#if defined(HX8369_HVGA)
&hx8369_hvga_lcm_drv,
#endif
#if defined(NT35510)
&nt35510_lcm_drv,
#endif
#if defined(NT35510_RGB_6575)
&nt35510_dpi_lcm_drv,
#endif
#if defined(NT35510_HVGA)
&nt35510_hvga_lcm_drv,
#endif
#if defined(NT35510_QVGA)
&nt35510_qvga_lcm_drv,
#endif
#if defined(NT35510_WVGA_DSI_CMD)
&nt35510_wvga_dsi_cmd_drv,
#endif
#if defined(NT35510_6517)
&nt35510_6517_lcm_drv,
#endif
#if defined(NT35510_DSI_CMD_6572)
&nt35510_dsi_cmd_6572_drv,
#endif
#if defined(NT35510_DSI_CMD_6572_HVGA)
&nt35510_dsi_cmd_6572_hvga_drv,
#endif
#if defined(NT35510_DSI_CMD_6572_FWVGA)
&nt35510_dsi_cmd_6572_fwvga_drv,
#endif
#if defined(NT35510_DSI_CMD_6572_QVGA)
&nt35510_dsi_cmd_6572_qvga_drv,
#endif
#if defined(NT35510_DSI_VDO_6572)
&nt35510_dsi_vdo_6572_drv,
#endif
#if defined(NT35510_DPI_6572)
&nt35510_dpi_6572_lcm_drv,
#endif
#if defined(NT35510_MCU_6572)
&nt35510_mcu_6572_lcm_drv,
#endif
#if defined(ILI9481)
&ili9481_lcm_drv,
#endif
#if defined(NT35582)
&nt35582_lcm_drv,
#endif
#if defined(S6D0170)
&s6d0170_lcm_drv,
#endif
#if defined(SPFD5461A)
&spfd5461a_lcm_drv,
#endif
#if defined(TA7601)
&ta7601_lcm_drv,
#endif
#if defined(TFT1P3037)
&tft1p3037_lcm_drv,
#endif
#if defined(HA5266)
&ha5266_lcm_drv,
#endif
#if defined(HSD070IDW1)
&hsd070idw1_lcm_drv,
#endif
#if defined(HX8363_6575_DSI)
&hx8363_6575_dsi_lcm_drv,
#endif
#if defined(HX8363_6575_DSI_HVGA)
&hx8363_6575_dsi_hvga_lcm_drv,
#endif
#if defined(HX8363B_WVGA_DSI_CMD)
&hx8363b_wvga_dsi_cmd_drv,
#endif
#if defined(LG4571)
&lg4571_lcm_drv,
#endif
#if defined(LG4573B_WVGA_DSI_VDO_LH430MV1)
&lg4573b_wvga_dsi_vdo_lh430mv1_drv,
#endif
#if defined(LVDS_WSVGA)
&lvds_wsvga_lcm_drv,
#endif
#if defined(LVDS_WSVGA_TI)
&lvds_wsvga_ti_lcm_drv,
#endif
#if defined(LVDS_WSVGA_TI_N)
&lvds_wsvga_ti_n_lcm_drv,
#endif
#if defined(NT35565_3D)
&nt35565_3d_lcm_drv,
#endif
#if defined(TM070DDH03)
&tm070ddh03_lcm_drv,
#endif
#if defined(R63303_IDISPLAY)
&r63303_idisplay_lcm_drv,
#endif
#if defined(HX8369B_DSI_VDO)
&hx8369b_dsi_vdo_lcm_drv,
#endif
#if defined(HX8369B_WVGA_DSI_VDO)
&hx8369b_wvga_dsi_vdo_drv,
#endif
#if defined(HX8369B_QHD_DSI_VDO)
&hx8389b_qhd_dsi_vdo_drv,
#endif
#if defined(GN_SSD2825_SMD_S6E8AA)
&gn_ssd2825_smd_s6e8aa,
#endif
#if defined(HX8369_TM_DSI)
&hx8369_dsi_tm_lcm_drv,
#endif
#if defined(HX8369_BLD_DSI)
&hx8369_dsi_bld_lcm_drv,
#endif
#if defined(HJ080IA)
&hj080ia_lcm_drv,
#endif
#if defined(HJ101NA02A)
&hj101na02a_lcm_drv,
#endif
#if defined(HJ101NA02A_8135)
&hj101na02a_8135_lcm_drv,
#endif
#if defined(HSD070PFW3)
&hsd070pfw3_lcm_drv,
#endif
#if defined(HSD070PFW3_8135)
&hsd070pfw3_8135_lcm_drv,
#endif
#if defined(EJ101IA)
&ej101ia_lcm_drv,
#endif
#if defined(SCF0700M48GGU02)
&scf0700m48ggu02_lcm_drv,
#endif
#if defined(OTM1280A_HD720_DSI_CMD)
&otm1280a_hd720_dsi_cmd_drv,
#endif
#if defined(OTM8018B_DSI_VDO)
&otm8018b_dsi_vdo_lcm_drv,
#endif
#if defined(NT35512_DSI_VDO)
&nt35512_dsi_vdo_lcm_drv,
#endif
#if defined(NT35512_WVGA_DSI_VDO_BOE)
&nt35512_wvga_dsi_vdo_boe_drv,
#endif
#if defined(HX8392A_DSI_CMD)
&hx8392a_dsi_cmd_lcm_drv,
#endif
#if defined(NT35516_QHD_DSI_CMD_IPSBOE)
&nt35516_qhd_dsi_cmd_ipsboe_lcm_drv,
#endif
#if defined(NT35516_QHD_DSI_CMD_IPSBOE_WVGA)
&nt35516_qhd_dsi_cmd_ipsboe_wvga_lcm_drv,
#endif
#if defined(NT35516_QHD_DSI_CMD_IPSBOE_FWVGA)
&nt35516_qhd_dsi_cmd_ipsboe_fwvga_lcm_drv,
#endif
#if defined(NT35516_QHD_DSI_CMD_IPS9K1431)
&nt35516_qhd_dsi_cmd_ips9k1431_drv,
#endif
#if defined(NT35516_QHD_DSI_CMD_TFT9K1342)
&nt35516_qhd_dsi_cmd_tft9k1342_drv,
#endif
#if defined(NT35516_QHD_DSI_VEDIO)
&nt35516_qhd_rav4_lcm_drv,
#endif
#if defined(BP070WS1)
&bp070ws1_lcm_drv,
#endif
#if defined(BP101WX1)
&bp101wx1_lcm_drv,
#endif
#if defined(BP101WX1_N)
&bp101wx1_n_lcm_drv,
#endif
#if defined(CM_N070ICE_DSI_VDO)
&cm_n070ice_dsi_vdo_lcm_drv,
#endif
#if defined(CM_OTC3108BH161_DSI_VDO)
&cm_otc3108bhv161_dsi_vdo_lcm_drv,
#endif
#if defined(NT35510_FWVGA)
&nt35510_fwvga_lcm_drv,
#endif
#if defined(R63311_FHD_DSI_VDO_SHARP)
&r63311_fhd_dsi_vdo_sharp_lcm_drv,
#endif
#if defined(R81592_HVGA_DSI_CMD)
&r81592_hvga_dsi_cmd_drv,
#endif
#if defined(RM68190_QHD_DSI_VDO)
&rm68190_dsi_vdo_lcm_drv,
#endif
#if defined(NT35596_FHD_DSI_VDO_TRULY)
&nt35596_fhd_dsi_vdo_truly_lcm_drv,
#endif
#if defined(NT35595_FHD_DSI_VDO_TRULY)
&nt35595_fhd_dsi_vdo_truly_lcm_drv,
#endif
#if defined(R63319_WQHD_DSI_VDO_TRULY)
&r63319_wqhd_dsi_vdo_truly_lcm_drv,
#endif
#if defined(NT35598_WQHD_DSI_VDO_TRULY)
&nt35598_wqhd_dsi_vdo_truly_lcm_drv,
#endif
#if defined(NT35595_FHD_DSI_CMD_TRULY_TPS65132)
&nt35595_fhd_dsi_cmd_truly_tps65132_lcm_drv,
#endif
#if defined(NT35595_FHD_DSI_CMD_TRULY_TPS65132_720P)
&nt35595_fhd_dsi_cmd_truly_tps65132_720p_lcm_drv,
#endif
#if defined(NT35595_FHD_DSI_CMD_TRULY)
&nt35595_fhd_dsi_cmd_truly_lcm_drv,
#endif
#if defined(NT35596_FHD_DSI_VDO_YASSY)
&nt35596_fhd_dsi_vdo_yassy_lcm_drv,
#endif
#if defined(AUO_B079XAT02_DSI_VDO)
&auo_b079xat02_dsi_vdo_lcm_drv,
#endif
#if defined(OTM9608_WVGA_DSI_CMD)
&otm9608_wvga_dsi_cmd_drv,
#endif
#if defined(NT35510_DBI_18BIT_GIONEE)
&nt35510_dbi_18bit_gionee_lcm_drv,
#endif
#if defined(OTM8009A_FWVGA_DSI_CMD_TIANMA)
&otm8009a_fwvga_dsi_cmd_tianma_lcm_drv,
#endif
#if defined(OTM8009A_FWVGA_DSI_VDO_TIANMA)
&otm8009a_fwvga_dsi_vdo_tianma_lcm_drv,
#endif
#if defined(HX8389B_QHD_DSI_VDO_TIANMA)
&hx8389b_qhd_dsi_vdo_tianma_lcm_drv,
#endif
#if defined(HX8389B_QHD_DSI_VDO_TIANMA055XDHP)
&hx8389b_qhd_dsi_vdo_tianma055xdhp_lcm_drv,
#endif
#if defined(CPT_CLAA101FP01_DSI_VDO)
&cpt_claa101fp01_dsi_vdo_lcm_drv,
#endif
#if defined(IT6151_EDP_DSI_VIDEO_SHARP)
&it6151_edp_dsi_video_sharp_lcm_drv,
#endif
#if defined(CPT_CLAP070WP03XG_SN65DSI83)
&cpt_clap070wp03xg_sn65dsi83_lcm_drv,
#endif
#if defined(NT35520_HD720_DSI_CMD_TM)
&nt35520_hd720_tm_lcm_drv,
#endif
#if defined(NT35520_HD720_DSI_CMD_BOE)
&nt35520_hd720_boe_lcm_drv,
#endif
#if defined(NT35521_HD720_DSI_VDO_BOE)
&nt35521_hd720_dsi_vdo_boe_lcm_drv,
#endif
#if defined(NT35521_HD720_DSI_VIDEO_TM)
&nt35521_hd720_tm_lcm_drv,
#endif
#if defined(H070D_18DM)
&h070d_18dm_lcm_drv,
#endif
#if defined(R69429_WUXGA_DSI_VDO)
&r69429_wuxga_dsi_vdo_lcm_drv,
#endif
#if defined(HX8394A_HD720_DSI_VDO_TIANMA)
&hx8394a_hd720_dsi_vdo_tianma_lcm_drv,
#endif
#if defined(R69429_WUXGA_DSI_CMD)
&r69429_wuxga_dsi_cmd_lcm_drv,
#endif
#if defined(RM68210_HD720_DSI_UFOE_CMD)
&rm68210_hd720_dsi_ufoe_cmd_lcm_drv,
#endif
#if defined(CPT_CLAP070WP03XG_LVDS)
&cpt_clap070wp03xg_lvds_lcm_drv,
#endif
#if defined(OTM8018B_DSI_VDO_LCSH72)
&otm8018b_dsi_vdo_lcsh72_lcm_drv,
#endif
#if defined(HX8369_DSI_CMD_6571)
&hx8369_dsi_cmd_6571_lcm_drv,
#endif
#if defined(HX8369_DSI_VDO_6571)
&hx8369_dsi_vdo_6571_lcm_drv,
#endif
#if defined(HX8369_DBI_6571)
&hx8369_dbi_6571_lcm_drv,
#endif
#if defined(HX8369_DPI_6571)
&hx8369_dpi_6571_lcm_drv,
#endif
#if defined(HX8389B_QHD_DSI_VDO_LGD)
&hx8389b_qhd_dsi_vdo_lgd_lcm_drv,
#endif
#if defined(NT35510_DSI_CMD_6571)
&nt35510_dsi_cmd_6571_lcm_drv,
#endif
#if defined(NT35510_DSI_CMD_6571_HVGA)
&nt35510_dsi_cmd_6571_hvga_lcm_drv,
#endif
#if defined(NT35510_DSI_CMD_6571_QVGA)
&nt35510_dsi_cmd_6571_qvga_lcm_drv,
#endif
#if defined(NT35510_DSI_VDO_6571)
&nt35510_dsi_vdo_6571_lcm_drv,
#endif
#if defined(NT35510_DBI_6571)
&nt35510_dbi_6571_lcm_drv,
#endif
#if defined(NT35510_DPI_6571)
&nt35510_dpi_6571_lcm_drv,
#endif
#if defined(NT35590_DSI_CMD_6571_FWVGA)
&nt35590_dsi_cmd_6571_fwvga_lcm_drv,
#endif
#if defined(NT35590_DSI_CMD_6571_QHD)
&nt35590_dsi_cmd_6571_qhd_lcm_drv,
#endif
#if defined(NT35517_QHD_DSI_VIDEO)
&nt35517_qhd_dsi_vdo_lcm_drv,
#endif
#if defined(IT6151_FHD_EDP_DSI_VIDEO_AUO)
&it6151_fhd_edp_dsi_video_auo_lcm_drv,
#endif
#if defined(A080EAN01_DSI_VDO)
&a080ean01_dsi_vdo_lcm_drv,
#endif
};
#define LCM_COMPILE_ASSERT(condition) LCM_COMPILE_ASSERT_X(condition, __LINE__)
#define LCM_COMPILE_ASSERT_X(condition, line) LCM_COMPILE_ASSERT_XX(condition, line)
#define LCM_COMPILE_ASSERT_XX(condition, line) char assertion_failed_at_line_##line[(condition)?1:-1]
unsigned int lcm_count = sizeof(lcm_driver_list)/sizeof(LCM_DRIVER*);
/*LCM_COMPILE_ASSERT(0 != sizeof(lcm_driver_list)/sizeof(LCM_DRIVER*));*/
#if defined(NT35520_HD720_DSI_CMD_TM) | defined(NT35520_HD720_DSI_CMD_BOE) | defined(NT35521_HD720_DSI_VDO_BOE) | defined(NT35521_HD720_DSI_VIDEO_TM)
#ifdef BUILD_LK
extern void mdelay(unsigned long msec);
#endif
static unsigned char lcd_id_pins_value = 0xFF;
/******************************************************************************
Function: which_lcd_module_triple
Description: read LCD ID PIN status,could identify three status:high¡¢low¡¢float
Input: none
Output: none
Return: LCD ID1|ID0 value
Others:
******************************************************************************/
unsigned char which_lcd_module_triple(void)
{
unsigned char high_read0 = 0;
unsigned char low_read0 = 0;
unsigned char high_read1 = 0;
unsigned char low_read1 = 0;
unsigned char lcd_id0 = 0;
unsigned char lcd_id1 = 0;
unsigned char lcd_id = 0;
//Solve Coverity scan warning : check return value
unsigned int ret = 0;
//only recognise once
if(0xFF != lcd_id_pins_value)
{
return lcd_id_pins_value;
}
//Solve Coverity scan warning : check return value
ret = mt_set_gpio_mode(GPIO_DISP_ID0_PIN, GPIO_MODE_00);
if(0 != ret)
{
LCD_DEBUG("ID0 mt_set_gpio_mode fail\n");
}
ret = mt_set_gpio_dir(GPIO_DISP_ID0_PIN, GPIO_DIR_IN);
if(0 != ret)
{
LCD_DEBUG("ID0 mt_set_gpio_dir fail\n");
}
ret = mt_set_gpio_pull_enable(GPIO_DISP_ID0_PIN, GPIO_PULL_ENABLE);
if(0 != ret)
{
LCD_DEBUG("ID0 mt_set_gpio_pull_enable fail\n");
}
ret = mt_set_gpio_mode(GPIO_DISP_ID1_PIN, GPIO_MODE_00);
if(0 != ret)
{
LCD_DEBUG("ID1 mt_set_gpio_mode fail\n");
}
ret = mt_set_gpio_dir(GPIO_DISP_ID1_PIN, GPIO_DIR_IN);
if(0 != ret)
{
LCD_DEBUG("ID1 mt_set_gpio_dir fail\n");
}
ret = mt_set_gpio_pull_enable(GPIO_DISP_ID1_PIN, GPIO_PULL_ENABLE);
if(0 != ret)
{
LCD_DEBUG("ID1 mt_set_gpio_pull_enable fail\n");
}
//pull down ID0 ID1 PIN
ret = mt_set_gpio_pull_select(GPIO_DISP_ID0_PIN,GPIO_PULL_DOWN);
if(0 != ret)
{
LCD_DEBUG("ID0 mt_set_gpio_pull_select->Down fail\n");
}
ret = mt_set_gpio_pull_select(GPIO_DISP_ID1_PIN,GPIO_PULL_DOWN);
if(0 != ret)
{
LCD_DEBUG("ID1 mt_set_gpio_pull_select->Down fail\n");
}
//delay 100ms , for discharging capacitance
mdelay(100);
//get ID0 ID1 status
low_read0 = mt_get_gpio_in(GPIO_DISP_ID0_PIN);
low_read1 = mt_get_gpio_in(GPIO_DISP_ID1_PIN);
//pull up ID0 ID1 PIN
ret = mt_set_gpio_pull_select(GPIO_DISP_ID0_PIN,GPIO_PULL_UP);
if(0 != ret)
{
LCD_DEBUG("ID0 mt_set_gpio_pull_select->UP fail\n");
}
ret = mt_set_gpio_pull_select(GPIO_DISP_ID1_PIN,GPIO_PULL_UP);
if(0 != ret)
{
LCD_DEBUG("ID1 mt_set_gpio_pull_select->UP fail\n");
}
//delay 100ms , for charging capacitance
mdelay(100);
//get ID0 ID1 status
high_read0 = mt_get_gpio_in(GPIO_DISP_ID0_PIN);
high_read1 = mt_get_gpio_in(GPIO_DISP_ID1_PIN);
if( low_read0 != high_read0 )
{
/*float status , pull down ID0 ,to prevent electric leakage*/
ret = mt_set_gpio_pull_select(GPIO_DISP_ID0_PIN,GPIO_PULL_DOWN);
if(0 != ret)
{
LCD_DEBUG("ID0 mt_set_gpio_pull_select->Down fail\n");
}
lcd_id0 = LCD_HW_ID_STATUS_FLOAT;
}
else if((LCD_HW_ID_STATUS_LOW == low_read0) && (LCD_HW_ID_STATUS_LOW == high_read0))
{
/*low status , pull down ID0 ,to prevent electric leakage*/
ret = mt_set_gpio_pull_select(GPIO_DISP_ID0_PIN,GPIO_PULL_DOWN);
if(0 != ret)
{
LCD_DEBUG("ID0 mt_set_gpio_pull_select->Down fail\n");
}
lcd_id0 = LCD_HW_ID_STATUS_LOW;
}
else if((LCD_HW_ID_STATUS_HIGH == low_read0) && (LCD_HW_ID_STATUS_HIGH == high_read0))
{
/*high status , pull up ID0 ,to prevent electric leakage*/
ret = mt_set_gpio_pull_select(GPIO_DISP_ID0_PIN,GPIO_PULL_UP);
if(0 != ret)
{
LCD_DEBUG("ID0 mt_set_gpio_pull_select->UP fail\n");
}
lcd_id0 = LCD_HW_ID_STATUS_HIGH;
}
else
{
LCD_DEBUG(" Read LCD_id0 error\n");
ret = mt_set_gpio_pull_select(GPIO_DISP_ID0_PIN,GPIO_PULL_DISABLE);
if(0 != ret)
{
LCD_DEBUG("ID0 mt_set_gpio_pull_select->Disbale fail\n");
}
lcd_id0 = LCD_HW_ID_STATUS_ERROR;
}
if( low_read1 != high_read1 )
{
/*float status , pull down ID1 ,to prevent electric leakage*/
ret = mt_set_gpio_pull_select(GPIO_DISP_ID1_PIN,GPIO_PULL_DOWN);
if(0 != ret)
{
LCD_DEBUG("ID1 mt_set_gpio_pull_select->Down fail\n");
}
lcd_id1 = LCD_HW_ID_STATUS_FLOAT;
}
else if((LCD_HW_ID_STATUS_LOW == low_read1) && (LCD_HW_ID_STATUS_LOW == high_read1))
{
/*low status , pull down ID1 ,to prevent electric leakage*/
ret = mt_set_gpio_pull_select(GPIO_DISP_ID1_PIN,GPIO_PULL_DOWN);
if(0 != ret)
{
LCD_DEBUG("ID1 mt_set_gpio_pull_select->Down fail\n");
}
lcd_id1 = LCD_HW_ID_STATUS_LOW;
}
else if((LCD_HW_ID_STATUS_HIGH == low_read1) && (LCD_HW_ID_STATUS_HIGH == high_read1))
{
/*high status , pull up ID1 ,to prevent electric leakage*/
ret = mt_set_gpio_pull_select(GPIO_DISP_ID1_PIN,GPIO_PULL_UP);
if(0 != ret)
{
LCD_DEBUG("ID1 mt_set_gpio_pull_select->UP fail\n");
}
lcd_id1 = LCD_HW_ID_STATUS_HIGH;
}
else
{
LCD_DEBUG(" Read LCD_id1 error\n");
ret = mt_set_gpio_pull_select(GPIO_DISP_ID1_PIN,GPIO_PULL_DISABLE);
if(0 != ret)
{
LCD_DEBUG("ID1 mt_set_gpio_pull_select->Disable fail\n");
}
lcd_id1 = LCD_HW_ID_STATUS_ERROR;
}
#ifdef BUILD_LK
dprintf(CRITICAL,"which_lcd_module_triple,lcd_id0:%d\n",lcd_id0);
dprintf(CRITICAL,"which_lcd_module_triple,lcd_id1:%d\n",lcd_id1);
#else
printk("which_lcd_module_triple,lcd_id0:%d\n",lcd_id0);
printk("which_lcd_module_triple,lcd_id1:%d\n",lcd_id1);
#endif
lcd_id = lcd_id0 | (lcd_id1 << 2);
#ifdef BUILD_LK
dprintf(CRITICAL,"which_lcd_module_triple,lcd_id:%d\n",lcd_id);
#else
printk("which_lcd_module_triple,lcd_id:%d\n",lcd_id);
#endif
lcd_id_pins_value = lcd_id;
return lcd_id;
}
#endif
arch/arm/mach-mt8127/ford/leds/Makefile
Executable
+5
View File
@@ -0,0 +1,5 @@
include $(srctree)/drivers/misc/mediatek/Makefile.custom
obj-$(CONFIG_MTK_LEDS) += mt65xx/
arch/arm/mach-mt8127/ford/leds/mt65xx/Makefile
Executable
+3
View File
@@ -0,0 +1,3 @@
include $(srctree)/drivers/misc/mediatek/Makefile.custom
obj-y := cust_leds.o
arch/arm/mach-mt8127/ford/leds/mt65xx/cust_leds.c
+128
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@@ -0,0 +1,128 @@
#include <cust_leds.h>
#include <cust_leds_def.h>
#include <mach/mt_pwm.h>
#include <linux/kernel.h>
#include <mach/pmic_mt6329_hw_bank1.h>
#include <mach/pmic_mt6329_sw_bank1.h>
#include <mach/pmic_mt6329_hw.h>
#include <mach/pmic_mt6329_sw.h>
#include <mach/upmu_common_sw.h>
#include <mach/upmu_hw.h>
extern int disp_bls_set_backlight(unsigned int level);
// Only support 64 levels of backlight (when lcd-backlight = MT65XX_LED_MODE_PWM)
#define BACKLIGHT_LEVEL_PWM_64_FIFO_MODE_SUPPORT 64
// Support 256 levels of backlight (when lcd-backlight = MT65XX_LED_MODE_PWM)
#define BACKLIGHT_LEVEL_PWM_256_SUPPORT 256
// Configure the support type "BACKLIGHT_LEVEL_PWM_256_SUPPORT" or "BACKLIGHT_LEVEL_PWM_64_FIFO_MODE_SUPPORT" !!
#define BACKLIGHT_LEVEL_PWM_MODE_CONFIG BACKLIGHT_LEVEL_PWM_256_SUPPORT
unsigned int Cust_GetBacklightLevelSupport_byPWM(void)
{
return BACKLIGHT_LEVEL_PWM_MODE_CONFIG;
}
unsigned int brightness_mapping(unsigned int level)
{
unsigned int mapped_level;
mapped_level = level;
return mapped_level;
}
/*
unsigned int Cust_SetBacklight(int level, int div)
{
kal_uint32 ret=0;
// mtkfb_set_backlight_pwm(div);
// mtkfb_set_backlight_level(brightness_mapping(level));
* To explain How to set these para for cust_led_list[] of led/backlight
* "name" para: led or backlight
* "mode" para:which mode for led/backlight
* such as:
* MT65XX_LED_MODE_NONE,
* MT65XX_LED_MODE_PWM,
* MT65XX_LED_MODE_GPIO,
* MT65XX_LED_MODE_PMIC,
* MT65XX_LED_MODE_CUST_LCM,
* MT65XX_LED_MODE_CUST_BLS_PWM
*
*"data" para: control methord for led/backlight
* such as:
* MT65XX_LED_PMIC_LCD_ISINK=0,
* MT65XX_LED_PMIC_NLED_ISINK0,
* MT65XX_LED_PMIC_NLED_ISINK1,
* MT65XX_LED_PMIC_NLED_ISINK2,
* MT65XX_LED_PMIC_NLED_ISINK3
*
*"PWM_config" para:PWM(AP side Or BLS module), by default setting{0,0,0,0,0} Or {0}
*struct PWM_config {
* int clock_source;
* int div;
* int low_duration;
* int High_duration;
* BOOL pmic_pad;//AP side PWM pin in PMIC chip (only 89 needs confirm); 1:yes 0:no(default)
*};
*-------------------------------------------------------------------------------------------
* for AP PWM setting as follow:
*1. PWM config data
* clock_source: clock source frequency, can be 0/1
* div: clock division, can be any value within 0~7 (i.e. 1/2^(div) = /1, /2, /4, /8, /16, /32, /64, /128)
* low_duration: only for BACKLIGHT_LEVEL_PWM_64_FIFO_MODE_SUPPORT
* High_duration: only for BACKLIGHT_LEVEL_PWM_64_FIFO_MODE_SUPPORT
*
*2. PWM freq.
* If BACKLIGHT_LEVEL_PWM_MODE_CONFIG = BACKLIGHT_LEVEL_PWM_256_SUPPORT,
* PWM freq. = clock source / 2^(div) / 256
*
* If BACKLIGHT_LEVEL_PWM_MODE_CONFIG = BACKLIGHT_LEVEL_PWM_64_FIFO_MODE_SUPPORT,
* PWM freq. = clock source / 2^(div) / [(High_duration+1)(Level')+(low_duration+1)(64 - Level')]
* = clock source / 2^(div) / [(High_duration+1)*64] (when low_duration = High_duration)
*Clock source:
* 0: block clock/1625 = 26M/1625 = 16K (MT6571)
* 1: block clock = 26M (MT6571)
*Div: 0~7
*
*For example, in MT6571, PWM_config = {1,1,0,0,0}
* ==> PWM freq. = 26M/2^1/256 = 50.78 KHz ( when BACKLIGHT_LEVEL_PWM_256_SUPPORT )
* ==> PWM freq. = 26M/2^1/(0+1)*64 = 203.13 KHz ( when BACKLIGHT_LEVEL_PWM_64_FIFO_MODE_SUPPORT )
*-------------------------------------------------------------------------------------------
* for BLS PWM setting as follow:
*1. PWM config data
* clock_source: clock source frequency, can be 0/1/2/3
* div: clock division, can be any value within 0~1023
* low_duration: non-use
* High_duration: non-use
* pmic_pad: non-use
*
*2. PWM freq.= clock source / (div + 1) /1024
*Clock source:
* 0: 26 MHz
* 1: 104 MHz
* 2: 124.8 MHz
* 3: 156 MHz
*Div: 0~1023
*
*By default, clock_source = 0 and div = 0 => PWM freq. = 26 KHz
*-------------------------------------------------------------------------------------------
*/
static struct cust_mt65xx_led cust_led_list[MT65XX_LED_TYPE_TOTAL] = {
{"red", MT65XX_LED_MODE_PMIC, MT65XX_LED_PMIC_NLED_ISINK2,{0}},
{"green", MT65XX_LED_MODE_PMIC, MT65XX_LED_PMIC_NLED_ISINK1,{0}},
{"blue", MT65XX_LED_MODE_PMIC, MT65XX_LED_PMIC_NLED_ISINK0,{0}},
{"jogball-backlight", MT65XX_LED_MODE_NONE, -1,{0}},
{"keyboard-backlight",MT65XX_LED_MODE_NONE, -1,{0}},
{"button-backlight", MT65XX_LED_MODE_NONE, -1,{0}},
{"lcd-backlight", MT65XX_LED_MODE_CUST_BLS_PWM, (int)disp_bls_set_backlight,{0,0,0,0,0}},
};
struct cust_mt65xx_led *get_cust_led_list(void)
{
return cust_led_list;
}
arch/arm/mach-mt8127/ford/leds/mt65xx/cust_leds.h
+20
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@@ -0,0 +1,20 @@
#ifndef _CUST_LEDS_H
#define _CUST_LEDS_H
#include <mach/mt_typedefs.h>
enum mt65xx_led_type
{
MT65XX_LED_TYPE_RED = 0,
MT65XX_LED_TYPE_GREEN,
MT65XX_LED_TYPE_BLUE,
MT65XX_LED_TYPE_JOGBALL,
MT65XX_LED_TYPE_KEYBOARD,
MT65XX_LED_TYPE_BUTTON,
MT65XX_LED_TYPE_LCD,
MT65XX_LED_TYPE_TOTAL,
};
#endif

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